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riscv: add Zvbb vector bit manipulation extension
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2
Makefile
2
Makefile
@ -101,7 +101,7 @@ SUBDIR_VARS := CLEANFILES FFLIBS HOSTPROGS TESTPROGS TOOLS \
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ARMV5TE-OBJS ARMV6-OBJS ARMV8-OBJS VFP-OBJS NEON-OBJS \
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ALTIVEC-OBJS VSX-OBJS MMX-OBJS X86ASM-OBJS \
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MIPSFPU-OBJS MIPSDSPR2-OBJS MIPSDSP-OBJS MSA-OBJS \
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MMI-OBJS LSX-OBJS LASX-OBJS RV-OBJS RVV-OBJS \
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MMI-OBJS LSX-OBJS LASX-OBJS RV-OBJS RVV-OBJS RVVB-OBJS \
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OBJS SLIBOBJS SHLIBOBJS STLIBOBJS HOSTOBJS TESTOBJS
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define RESET
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3
configure
vendored
3
configure
vendored
@ -2222,6 +2222,7 @@ ARCH_EXT_LIST_PPC="
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ARCH_EXT_LIST_RISCV="
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rv
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rvv
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rv_zvbb
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"
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ARCH_EXT_LIST_X86="
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@ -2760,6 +2761,7 @@ power8_deps="vsx"
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rv_deps="riscv"
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rvv_deps="rv"
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rv_zvbb_deps="rvv"
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loongson2_deps="mips"
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loongson3_deps="mips"
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@ -6384,6 +6386,7 @@ elif enabled riscv; then
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enabled rv && check_inline_asm rv '".option arch, +zbb\nrev8 t0, t1"'
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enabled rvv && check_inline_asm rvv '".option arch, +v\nvsetivli zero, 0, e8, m1, ta, ma"'
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enabled rv_zvbb && check_inline_asm rv_zvbb '".option arch, +zvbb\nvclz.v v0, v8"'
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elif enabled x86; then
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@ -2,6 +2,9 @@ The last version increases of all libraries were on 2024-03-07
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API changes, most recent first:
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2024-05-10 - xxxxxxxxx - lavu 59.18.100 - cpu.h
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Add AV_CPU_FLAG_RV_ZVBB.
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2024-05-04 - xxxxxxxxxx - lavu 59.17.100 - opt.h
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Add AV_OPT_TYPE_UINT and av_opt_eval_uint().
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@ -17,6 +17,7 @@ OBJS-$(HAVE_VSX) += $(VSX-OBJS) $(VSX-OBJS-yes)
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OBJS-$(HAVE_RV) += $(RV-OBJS) $(RV-OBJS-yes)
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OBJS-$(HAVE_RVV) += $(RVV-OBJS) $(RVV-OBJS-yes)
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OBJS-$(HAVE_RV_ZVBB) += $(RVVB-OBJS) $(RVVB-OBJS-yes)
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OBJS-$(HAVE_MMX) += $(MMX-OBJS) $(MMX-OBJS-yes)
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OBJS-$(HAVE_X86ASM) += $(X86ASM-OBJS) $(X86ASM-OBJS-yes)
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@ -192,6 +192,7 @@ int av_parse_cpu_caps(unsigned *flags, const char *s)
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{ "zve64d", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F64 }, .unit = "flags" },
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{ "zba", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB_ADDR }, .unit = "flags" },
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{ "zbb", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB_BASIC }, .unit = "flags" },
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{ "zvbb", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RV_ZVBB }, .unit = "flags" },
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#endif
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{ NULL },
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};
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@ -90,6 +90,7 @@
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#define AV_CPU_FLAG_RVV_F64 (1 << 6) ///< Vectors of double's
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#define AV_CPU_FLAG_RVB_BASIC (1 << 7) ///< Basic bit-manipulations
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#define AV_CPU_FLAG_RVB_ADDR (1 << 8) ///< Address bit-manipulations
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#define AV_CPU_FLAG_RV_ZVBB (1 << 9) ///< Vector basic bit-manipulations
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/**
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* Return the flags which specify extensions supported by the CPU.
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@ -94,6 +94,7 @@ static const struct {
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{ AV_CPU_FLAG_RVV_F32, "zve32f" },
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{ AV_CPU_FLAG_RVV_I64, "zve64x" },
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{ AV_CPU_FLAG_RVV_F64, "zve64d" },
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{ AV_CPU_FLAG_RV_ZVBB, "zvbb" },
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#endif
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{ 0 }
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};
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@ -285,6 +285,7 @@ static const struct {
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{ "RVVf32", "rvv_f32", AV_CPU_FLAG_RVV_F32 },
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{ "RVVi64", "rvv_i64", AV_CPU_FLAG_RVV_I64 },
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{ "RVVf64", "rvv_f64", AV_CPU_FLAG_RVV_F64 },
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{ "RV_Zvbb", "rv_zvbb", AV_CPU_FLAG_RV_ZVBB },
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#elif ARCH_MIPS
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{ "MMI", "mmi", AV_CPU_FLAG_MMI },
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{ "MSA", "msa", AV_CPU_FLAG_MSA },
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