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aarch64/vvc: Add w_avg
w_avg_8_2x2_c: 0.0 ( 0.00x) w_avg_8_2x2_neon: 0.0 ( 0.00x) w_avg_8_4x4_c: 0.2 ( 1.00x) w_avg_8_4x4_neon: 0.0 ( 0.00x) w_avg_8_8x8_c: 1.2 ( 1.00x) w_avg_8_8x8_neon: 0.2 ( 5.00x) w_avg_8_16x16_c: 4.2 ( 1.00x) w_avg_8_16x16_neon: 0.8 ( 5.67x) w_avg_8_32x32_c: 16.2 ( 1.00x) w_avg_8_32x32_neon: 2.5 ( 6.50x) w_avg_8_64x64_c: 64.5 ( 1.00x) w_avg_8_64x64_neon: 9.0 ( 7.17x) w_avg_8_128x128_c: 269.5 ( 1.00x) w_avg_8_128x128_neon: 35.5 ( 7.59x) w_avg_10_2x2_c: 0.2 ( 1.00x) w_avg_10_2x2_neon: 0.2 ( 1.00x) w_avg_10_4x4_c: 0.2 ( 1.00x) w_avg_10_4x4_neon: 0.2 ( 1.00x) w_avg_10_8x8_c: 1.0 ( 1.00x) w_avg_10_8x8_neon: 0.2 ( 4.00x) w_avg_10_16x16_c: 4.2 ( 1.00x) w_avg_10_16x16_neon: 0.8 ( 5.67x) w_avg_10_32x32_c: 16.2 ( 1.00x) w_avg_10_32x32_neon: 2.5 ( 6.50x) w_avg_10_64x64_c: 66.2 ( 1.00x) w_avg_10_64x64_neon: 10.0 ( 6.62x) w_avg_10_128x128_c: 277.8 ( 1.00x) w_avg_10_128x128_neon: 39.8 ( 6.99x) w_avg_12_2x2_c: 0.0 ( 0.00x) w_avg_12_2x2_neon: 0.2 ( 0.00x) w_avg_12_4x4_c: 0.2 ( 1.00x) w_avg_12_4x4_neon: 0.0 ( 0.00x) w_avg_12_8x8_c: 1.2 ( 1.00x) w_avg_12_8x8_neon: 0.5 ( 2.50x) w_avg_12_16x16_c: 4.8 ( 1.00x) w_avg_12_16x16_neon: 0.8 ( 6.33x) w_avg_12_32x32_c: 17.0 ( 1.00x) w_avg_12_32x32_neon: 2.8 ( 6.18x) w_avg_12_64x64_c: 64.0 ( 1.00x) w_avg_12_64x64_neon: 10.0 ( 6.40x) w_avg_12_128x128_c: 269.2 ( 1.00x) w_avg_12_128x128_neon: 42.0 ( 6.41x) Signed-off-by: Zhao Zhili <zhilizhao@tencent.com>
This commit is contained in:
Zhao Zhili
Nuo Mi
parent
76eb3e5ff3
commit
0ba9e8d0d4
@ -52,6 +52,39 @@ void ff_vvc_avg_12_neon(uint8_t *dst, ptrdiff_t dst_stride,
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const int16_t *src0, const int16_t *src1, int width,
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int height);
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void ff_vvc_w_avg_8_neon(uint8_t *_dst, ptrdiff_t _dst_stride,
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const int16_t *src0, const int16_t *src1,
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int width, int height,
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uintptr_t w0_w1, uintptr_t offset_shift);
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void ff_vvc_w_avg_10_neon(uint8_t *_dst, ptrdiff_t _dst_stride,
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const int16_t *src0, const int16_t *src1,
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int width, int height,
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uintptr_t w0_w1, uintptr_t offset_shift);
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void ff_vvc_w_avg_12_neon(uint8_t *_dst, ptrdiff_t _dst_stride,
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const int16_t *src0, const int16_t *src1,
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int width, int height,
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uintptr_t w0_w1, uintptr_t offset_shift);
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/* When passing arguments to functions, Apple platforms diverge from the ARM64
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* standard ABI for functions that require passing arguments on the stack. To
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* simplify portability in the assembly function interface, use a different
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* function signature that doesn't require passing arguments on the stack.
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*/
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#define W_AVG_FUN(bit_depth) \
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static void vvc_w_avg_ ## bit_depth(uint8_t *dst, ptrdiff_t dst_stride, \
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const int16_t *src0, const int16_t *src1, int width, int height, \
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int denom, int w0, int w1, int o0, int o1) \
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{ \
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int shift = denom + FFMAX(3, 15 - bit_depth); \
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int offset = ((o0 + o1) * (1 << (bit_depth - 8)) + 1) * (1 << (shift - 1)); \
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uintptr_t w0_w1 = ((uintptr_t)w0 << 32) | (uint32_t)w1; \
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uintptr_t offset_shift = ((uintptr_t)offset << 32) | (uint32_t)shift; \
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ff_vvc_w_avg_ ## bit_depth ## _neon(dst, dst_stride, src0, src1, width, height, w0_w1, offset_shift); \
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}
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W_AVG_FUN(8)
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W_AVG_FUN(10)
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W_AVG_FUN(12)
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void ff_vvc_dsp_init_aarch64(VVCDSPContext *const c, const int bd)
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{
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int cpu_flags = av_get_cpu_flags();
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@ -123,6 +156,7 @@ void ff_vvc_dsp_init_aarch64(VVCDSPContext *const c, const int bd)
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c->inter.put_uni_w[0][6][0][0] = ff_vvc_put_pel_uni_w_pixels128_8_neon;
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c->inter.avg = ff_vvc_avg_8_neon;
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c->inter.w_avg = vvc_w_avg_8;
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for (int i = 0; i < FF_ARRAY_ELEMS(c->sao.band_filter); i++)
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c->sao.band_filter[i] = ff_h26x_sao_band_filter_8x8_8_neon;
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@ -163,11 +197,13 @@ void ff_vvc_dsp_init_aarch64(VVCDSPContext *const c, const int bd)
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}
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} else if (bd == 10) {
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c->inter.avg = ff_vvc_avg_10_neon;
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c->inter.w_avg = vvc_w_avg_10;
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c->alf.filter[LUMA] = alf_filter_luma_10_neon;
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c->alf.filter[CHROMA] = alf_filter_chroma_10_neon;
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} else if (bd == 12) {
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c->inter.avg = ff_vvc_avg_12_neon;
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c->inter.w_avg = vvc_w_avg_12;
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c->alf.filter[LUMA] = alf_filter_luma_12_neon;
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c->alf.filter[CHROMA] = alf_filter_chroma_12_neon;
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@ -22,9 +22,9 @@
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#define VVC_MAX_PB_SIZE 128
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.macro vvc_avg, bit_depth
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.macro vvc_avg type, bit_depth
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.macro vvc_avg_\bit_depth\()_2_4, tap
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.macro vvc_\type\()_\bit_depth\()_2_4 tap
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.if \tap == 2
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ldr s0, [src0]
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ldr s2, [src1]
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@ -32,9 +32,19 @@
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ldr d0, [src0]
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ldr d2, [src1]
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.endif
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.ifc \type, avg
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saddl v4.4s, v0.4h, v2.4h
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add v4.4s, v4.4s, v16.4s
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sqshrn v4.4h, v4.4s, #(15 - \bit_depth)
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.else
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mov v4.16b, v16.16b
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smlal v4.4s, v0.4h, v19.4h
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smlal v4.4s, v2.4h, v20.4h
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sqshl v4.4s, v4.4s, v22.4s
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sqxtn v4.4h, v4.4s
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.endif
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.if \bit_depth == 8
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sqxtun v4.8b, v4.8h
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.if \tap == 2
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@ -57,7 +67,7 @@
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add dst, dst, dst_stride
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.endm
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function ff_vvc_avg_\bit_depth\()_neon, export=1
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function ff_vvc_\type\()_\bit_depth\()_neon, export=1
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dst .req x0
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dst_stride .req x1
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src0 .req x2
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@ -67,42 +77,64 @@ function ff_vvc_avg_\bit_depth\()_neon, export=1
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mov x10, #(VVC_MAX_PB_SIZE * 2)
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cmp width, #8
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.if \bit_depth == 8
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movi v16.4s, #64
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.ifc \type, avg
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movi v16.4s, #(1 << (14 - \bit_depth))
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.else
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.if \bit_depth == 10
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mov w6, #1023
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movi v16.4s, #16
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.else
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mov w6, #4095
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movi v16.4s, #4
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.endif
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lsr x11, x6, #32 // weight0
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mov w12, w6 // weight1
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lsr x13, x7, #32 // offset
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mov w14, w7 // shift
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dup v19.8h, w11
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neg w14, w14 // so we can use sqshl
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dup v20.8h, w12
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dup v16.4s, w13
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dup v22.4s, w14
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.endif // avg
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.if \bit_depth >= 10
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// clip pixel
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mov w6, #((1 << \bit_depth) - 1)
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movi v18.8h, #0
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dup v17.8h, w6
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.endif
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b.eq 8f
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b.hi 16f
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cmp width, #4
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b.eq 4f
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2: // width == 2
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subs height, height, #1
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vvc_avg_\bit_depth\()_2_4 2
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vvc_\type\()_\bit_depth\()_2_4 2
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b.ne 2b
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b 32f
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4: // width == 4
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subs height, height, #1
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vvc_avg_\bit_depth\()_2_4 4
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vvc_\type\()_\bit_depth\()_2_4 4
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b.ne 4b
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b 32f
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8: // width == 8
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ld1 {v0.8h}, [src0], x10
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ld1 {v2.8h}, [src1], x10
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.ifc \type, avg
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saddl v4.4s, v0.4h, v2.4h
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saddl2 v5.4s, v0.8h, v2.8h
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add v4.4s, v4.4s, v16.4s
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add v5.4s, v5.4s, v16.4s
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sqshrn v4.4h, v4.4s, #(15 - \bit_depth)
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sqshrn2 v4.8h, v5.4s, #(15 - \bit_depth)
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.else
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mov v4.16b, v16.16b
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mov v5.16b, v16.16b
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smlal v4.4s, v0.4h, v19.4h
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smlal v4.4s, v2.4h, v20.4h
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smlal2 v5.4s, v0.8h, v19.8h
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smlal2 v5.4s, v2.8h, v20.8h
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sqshl v4.4s, v4.4s, v22.4s
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sqshl v5.4s, v5.4s, v22.4s
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sqxtn v4.4h, v4.4s
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sqxtn2 v4.8h, v5.4s
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.endif
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subs height, height, #1
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.if \bit_depth == 8
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sqxtun v4.8b, v4.8h
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@ -122,6 +154,7 @@ function ff_vvc_avg_\bit_depth\()_neon, export=1
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17:
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ldp q0, q1, [x7], #32
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ldp q2, q3, [x8], #32
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.ifc \type, avg
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saddl v4.4s, v0.4h, v2.4h
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saddl2 v5.4s, v0.8h, v2.8h
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saddl v6.4s, v1.4h, v3.4h
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@ -134,6 +167,28 @@ function ff_vvc_avg_\bit_depth\()_neon, export=1
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sqshrn2 v4.8h, v5.4s, #(15 - \bit_depth)
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sqshrn v6.4h, v6.4s, #(15 - \bit_depth)
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sqshrn2 v6.8h, v7.4s, #(15 - \bit_depth)
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.else // avg
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mov v4.16b, v16.16b
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mov v5.16b, v16.16b
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mov v6.16b, v16.16b
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mov v7.16b, v16.16b
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smlal v4.4s, v0.4h, v19.4h
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smlal v4.4s, v2.4h, v20.4h
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smlal2 v5.4s, v0.8h, v19.8h
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smlal2 v5.4s, v2.8h, v20.8h
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smlal v6.4s, v1.4h, v19.4h
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smlal v6.4s, v3.4h, v20.4h
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smlal2 v7.4s, v1.8h, v19.8h
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smlal2 v7.4s, v3.8h, v20.8h
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sqshl v4.4s, v4.4s, v22.4s
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sqshl v5.4s, v5.4s, v22.4s
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sqshl v6.4s, v6.4s, v22.4s
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sqshl v7.4s, v7.4s, v22.4s
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sqxtn v4.4h, v4.4s
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sqxtn v6.4h, v6.4s
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sqxtn2 v4.8h, v5.4s
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sqxtn2 v6.8h, v7.4s
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.endif // w_avg
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subs w6, w6, #16
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.if \bit_depth == 8
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sqxtun v4.8b, v4.8h
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@ -155,9 +210,19 @@ function ff_vvc_avg_\bit_depth\()_neon, export=1
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b.ne 16b
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32:
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ret
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.unreq dst
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.unreq dst_stride
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.unreq src0
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.unreq src1
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.unreq width
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.unreq height
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endfunc
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.endm
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vvc_avg 8
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vvc_avg 10
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vvc_avg 12
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vvc_avg avg, 8
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vvc_avg avg, 10
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vvc_avg avg, 12
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vvc_avg w_avg, 8
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vvc_avg w_avg, 10
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vvc_avg w_avg, 12
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