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lavu/riscv: CPU flag for the Zbb extension

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Unfortunately, it is common, and will remain so, that the Bit
manipulations are not enabled at compilation time. This is an official
policy for Debian ports in general (though they do not support RISC-V
officially as of yet) to stick to the minimal target baseline, which
does not include the B extension or even its Zbb subset.

For inline helpers (CPOP, REV8), compiler builtins (CTZ, CLZ) or
even plain C code (MIN, MAX, MINU, MAXU), run-time detection seems
impractical. But at least it can work for the byte-swap DSP functions.
This commit is contained in:
Rémi Denis-Courmont 2022-10-02 14:54:58 +03:00 committed by Lynne
parent b25c6a5704
commit 37d5ddc317
4 changed files with 9 additions and 0 deletions
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1
libavutil/cpu.c
View File

@ -188,6 +188,7 @@ int av_parse_cpu_caps(unsigned *flags, const char *s)
{ "rvv-f32", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F32 }, .unit = "flags" },
{ "rvv-i64", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_I64 }, .unit = "flags" },
{ "rvv", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F64 }, .unit = "flags" },
{ "rvb-basic",NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB_BASIC }, .unit = "flags" },
#endif
{ NULL },
};

1
libavutil/cpu.h
View File

@ -86,6 +86,7 @@
#define AV_CPU_FLAG_RVV_F32 (1 << 4) ///< Vectors of float's */
#define AV_CPU_FLAG_RVV_I64 (1 << 5) ///< Vectors of 64-bit int's */
#define AV_CPU_FLAG_RVV_F64 (1 << 6) ///< Vectors of double's
#define AV_CPU_FLAG_RVB_BASIC (1 << 7) ///< Basic bit-manipulations
/**
* Return the flags which specify extensions supported by the CPU.

6
libavutil/riscv/cpu.c
View File

@ -40,6 +40,8 @@ int ff_get_cpu_flags_riscv(void)
ret |= AV_CPU_FLAG_RVF;
if (hwcap & HWCAP_RV('D'))
ret |= AV_CPU_FLAG_RVD;
if (hwcap & HWCAP_RV('B'))
ret |= AV_CPU_FLAG_RVB_BASIC;
/* The V extension implies all Zve* functional subsets */
if (hwcap & HWCAP_RV('V'))
@ -57,6 +59,10 @@ int ff_get_cpu_flags_riscv(void)
#endif
#endif
#ifdef __riscv_zbb
ret |= AV_CPU_FLAG_RVB_BASIC;
#endif
/* If RV-V is enabled statically at compile-time, check the details. */
#ifdef __riscv_vectors
ret |= AV_CPU_FLAG_RVV_I32;

1
tests/checkasm/checkasm.c
View File

@ -240,6 +240,7 @@ static const struct {
{ "RVVf32", "rvv_f32", AV_CPU_FLAG_RVV_F32 },
{ "RVVi64", "rvv_i64", AV_CPU_FLAG_RVV_I64 },
{ "RVVf64", "rvv_f64", AV_CPU_FLAG_RVV_F64 },
{ "RVBbasic", "rvb_b", AV_CPU_FLAG_RVB_BASIC },
#elif ARCH_MIPS
{ "MMI", "mmi", AV_CPU_FLAG_MMI },
{ "MSA", "msa", AV_CPU_FLAG_MSA },