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x86/hevc_sao: simplify sao_edge_filter 10/12bit
Reviewed-by: Michael Niedermayer <michaelni@gmx.at> Reviewed-by: Christophe Gisquet <christophe.gisquet@gmail.com> Signed-off-by: James Almer <jamrial@gmail.com>
This commit is contained in:
James Almer
parent
34b2bd03cf
commit
3ff2beff65
@ -221,46 +221,6 @@ HEVC_SAO_BAND_FILTER 12, 64, 4
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add b_strideq, tmpq
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%endmacro
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%macro HEVC_SAO_EDGE_FILTER_COMPUTE 0
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PMINUW m4, m1, m2, m6
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PMINUW m5, m1, m3, m7
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pcmpeqw m2, m4
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pcmpeqw m3, m5
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pcmpeqw m4, m1
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pcmpeqw m5, m1
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psubw m4, m2
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psubw m5, m3
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paddw m4, m5
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pcmpeqw m2, m4, [pw_m2]
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%if ARCH_X86_64
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pcmpeqw m3, m4, m13
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pcmpeqw m5, m4, m0
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pcmpeqw m6, m4, m14
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pcmpeqw m7, m4, m15
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pand m2, m8
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pand m3, m9
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pand m5, m10
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pand m6, m11
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pand m7, m12
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%else
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pcmpeqw m3, m4, [pw_m1]
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pcmpeqw m5, m4, m0
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pcmpeqw m6, m4, [pw_1]
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pcmpeqw m7, m4, [pw_2]
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pand m2, [rsp+MMSIZE*0]
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pand m3, [rsp+MMSIZE*1]
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pand m5, [rsp+MMSIZE*2]
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pand m6, [rsp+MMSIZE*3]
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pand m7, [rsp+MMSIZE*4]
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%endif
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paddw m2, m3
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paddw m5, m6
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paddw m2, m7
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paddw m2, m1
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paddw m2, m5
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%endmacro
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;void ff_hevc_sao_edge_filter_<width>_<depth>_<opt>(uint8_t *_dst, uint8_t *_src, ptrdiff_t stride_dst, int16_t *sao_offset_val,
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; int eo, int width, int height);
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%macro HEVC_SAO_EDGE_FILTER 3
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@ -274,7 +234,6 @@ cglobal hevc_sao_edge_filter_%2_%1, 4, 9, 16, dst, src, dststride, offset, eo, a
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%else ; ARCH_X86_32
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cglobal hevc_sao_edge_filter_%2_%1, 1, 6, 8, 5*mmsize, dst, src, dststride, a_stride, b_stride, height
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%assign MMSIZE mmsize
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%define eoq srcq
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%define tmpq heightq
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%define tmp2q dststrideq
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@ -325,54 +284,53 @@ cglobal hevc_sao_edge_filter_%2_%1, 1, 6, 8, 5*mmsize, dst, src, dststride, a_st
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align 16
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.loop:
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%if %2 == 8
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mova m1, [srcq]
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movu m2, [srcq+a_strideq]
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movu m3, [srcq+b_strideq]
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HEVC_SAO_EDGE_FILTER_COMPUTE
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CLIPW m2, m0, [pw_mask %+ %1]
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movu [dstq], m2
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%endif
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%assign i 0
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%rep %3
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mova m1, [srcq + i]
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movu m2, [srcq+a_strideq + i]
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movu m3, [srcq+b_strideq + i]
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HEVC_SAO_EDGE_FILTER_COMPUTE
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PMINUW m4, m1, m2, m6
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PMINUW m5, m1, m3, m7
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pcmpeqw m2, m4
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pcmpeqw m3, m5
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pcmpeqw m4, m1
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pcmpeqw m5, m1
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psubw m4, m2
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psubw m5, m3
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paddw m4, m5
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pcmpeqw m2, m4, [pw_m2]
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%if ARCH_X86_64
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pcmpeqw m3, m4, m13
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pcmpeqw m5, m4, m0
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pcmpeqw m6, m4, m14
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pcmpeqw m7, m4, m15
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pand m2, m8
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pand m3, m9
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pand m5, m10
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pand m6, m11
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pand m7, m12
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%else
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pcmpeqw m3, m4, [pw_m1]
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pcmpeqw m5, m4, m0
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pcmpeqw m6, m4, [pw_1]
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pcmpeqw m7, m4, [pw_2]
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pand m2, [rsp+mmsize*0]
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pand m3, [rsp+mmsize*1]
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pand m5, [rsp+mmsize*2]
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pand m6, [rsp+mmsize*3]
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pand m7, [rsp+mmsize*4]
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%endif
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paddw m2, m3
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paddw m5, m6
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paddw m2, m7
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paddw m2, m1
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paddw m2, m5
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CLIPW m2, m0, [pw_mask %+ %1]
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mova [dstq + i], m2
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mova m1, [srcq + i + mmsize]
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movu m2, [srcq+a_strideq + i + mmsize]
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movu m3, [srcq+b_strideq + i + mmsize]
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HEVC_SAO_EDGE_FILTER_COMPUTE
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CLIPW m2, m0, [pw_mask %+ %1]
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mova [dstq + i + mmsize], m2
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%assign i i+mmsize*2
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%assign i i+mmsize
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%endrep
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%if %2 == 48
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INIT_XMM cpuname
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mova m1, [srcq + i]
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movu m2, [srcq+a_strideq + i]
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movu m3, [srcq+b_strideq + i]
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HEVC_SAO_EDGE_FILTER_COMPUTE
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CLIPW m2, m0, [pw_mask %+ %1]
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mova [dstq + i], m2
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mova m1, [srcq + i + mmsize]
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movu m2, [srcq+a_strideq + i + mmsize]
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movu m3, [srcq+b_strideq + i + mmsize]
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HEVC_SAO_EDGE_FILTER_COMPUTE
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CLIPW m2, m0, [pw_mask %+ %1]
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mova [dstq + i + mmsize], m2
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%if cpuflag(avx2)
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INIT_YMM cpuname
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%endif
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%endif
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add dstq, dststrideq
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add srcq, EDGE_SRCSTRIDE
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dec heightd
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@ -381,25 +339,25 @@ INIT_YMM cpuname
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%endmacro
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INIT_XMM sse2
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HEVC_SAO_EDGE_FILTER 10, 8, 0
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HEVC_SAO_EDGE_FILTER 10, 16, 1
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HEVC_SAO_EDGE_FILTER 10, 32, 2
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HEVC_SAO_EDGE_FILTER 10, 48, 2
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HEVC_SAO_EDGE_FILTER 10, 64, 4
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HEVC_SAO_EDGE_FILTER 10, 8, 1
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HEVC_SAO_EDGE_FILTER 10, 16, 2
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HEVC_SAO_EDGE_FILTER 10, 32, 4
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HEVC_SAO_EDGE_FILTER 10, 48, 6
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HEVC_SAO_EDGE_FILTER 10, 64, 8
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HEVC_SAO_EDGE_FILTER 12, 8, 0
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HEVC_SAO_EDGE_FILTER 12, 16, 1
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HEVC_SAO_EDGE_FILTER 12, 32, 2
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HEVC_SAO_EDGE_FILTER 12, 48, 2
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HEVC_SAO_EDGE_FILTER 12, 64, 4
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HEVC_SAO_EDGE_FILTER 12, 8, 1
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HEVC_SAO_EDGE_FILTER 12, 16, 2
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HEVC_SAO_EDGE_FILTER 12, 32, 4
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HEVC_SAO_EDGE_FILTER 12, 48, 6
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HEVC_SAO_EDGE_FILTER 12, 64, 8
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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HEVC_SAO_EDGE_FILTER 10, 32, 1
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HEVC_SAO_EDGE_FILTER 10, 48, 1
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HEVC_SAO_EDGE_FILTER 10, 64, 2
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HEVC_SAO_EDGE_FILTER 10, 32, 2
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HEVC_SAO_EDGE_FILTER 10, 48, 3
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HEVC_SAO_EDGE_FILTER 10, 64, 4
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HEVC_SAO_EDGE_FILTER 12, 32, 1
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HEVC_SAO_EDGE_FILTER 12, 48, 1
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HEVC_SAO_EDGE_FILTER 12, 64, 2
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HEVC_SAO_EDGE_FILTER 12, 32, 2
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HEVC_SAO_EDGE_FILTER 12, 48, 3
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HEVC_SAO_EDGE_FILTER 12, 64, 4
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%endif
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