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lavu/riscv: remove bespoke SH{1,2,3}ADD assembler

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configure checks that the assembler supports the B extension (or rather
its constituents) anyway. These macros were dodging sanity checks for
unsupported instructions and nothing else.
This commit is contained in:
Rémi Denis-Courmont 2024-07-22 20:24:30 +03:00
parent 5f10173fa1
commit 529d423012
1 changed files with 0 additions and 19 deletions
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19
libavutil/riscv/asm.S
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@ -83,25 +83,6 @@
.endm
.endm
#if !defined (__riscv_zba)
/* SH{1,2,3}ADD definitions for pre-Zba assemblers */
.macro shnadd n, rd, rs1, rs2
.insn r OP, 2 * \n, 16, \rd, \rs1, \rs2
.endm
.macro sh1add rd, rs1, rs2
shnadd 1, \rd, \rs1, \rs2
.endm
.macro sh2add rd, rs1, rs2
shnadd 2, \rd, \rs1, \rs2
.endm
.macro sh3add rd, rs1, rs2
shnadd 3, \rd, \rs1, \rs2
.endm
#endif
#if defined (__riscv_v_elen)
# define RV_V_ELEN __riscv_v_elen
#else