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checkasm: arm: Make the indentation consistent with other files
This makes it easier to share code with e.g. the dav1d implementation of checkasm. Signed-off-by: Martin Storsjö <martin@martin.st>
This commit is contained in:
Martin Storsjö
parent
07948f3d38
commit
89cf9e1fb6
@ -23,29 +23,29 @@
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#include "libavutil/aarch64/asm.S"
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const register_init, align=4
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.quad 0x21f86d66c8ca00ce
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.quad 0x75b6ba21077c48ad
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.quad 0xed56bb2dcb3c7736
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.quad 0x8bda43d3fd1a7e06
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.quad 0xb64a9c9e5d318408
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.quad 0xdf9a54b303f1d3a3
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.quad 0x4a75479abd64e097
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.quad 0x249214109d5d1c88
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.quad 0x1a1b2550a612b48c
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.quad 0x79445c159ce79064
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.quad 0x2eed899d5a28ddcd
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.quad 0x86b2536fcd8cf636
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.quad 0xb0856806085e7943
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.quad 0x3f2bf84fc0fcca4e
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.quad 0xacbd382dcf5b8de2
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.quad 0xd229e1f5b281303f
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.quad 0x71aeaff20b095fd9
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.quad 0xab63e2e11fa38ed9
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.quad 0x21f86d66c8ca00ce
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.quad 0x75b6ba21077c48ad
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.quad 0xed56bb2dcb3c7736
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.quad 0x8bda43d3fd1a7e06
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.quad 0xb64a9c9e5d318408
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.quad 0xdf9a54b303f1d3a3
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.quad 0x4a75479abd64e097
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.quad 0x249214109d5d1c88
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.quad 0x1a1b2550a612b48c
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.quad 0x79445c159ce79064
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.quad 0x2eed899d5a28ddcd
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.quad 0x86b2536fcd8cf636
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.quad 0xb0856806085e7943
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.quad 0x3f2bf84fc0fcca4e
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.quad 0xacbd382dcf5b8de2
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.quad 0xd229e1f5b281303f
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.quad 0x71aeaff20b095fd9
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.quad 0xab63e2e11fa38ed9
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endconst
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const error_message
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.asciz "failed to preserve register"
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.asciz "failed to preserve register"
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endconst
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@ -55,103 +55,103 @@ endconst
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#define CLOBBER_STACK ((8*MAX_ARGS + 15) & ~15)
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function checkasm_stack_clobber, export=1
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mov x3, sp
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mov x2, #CLOBBER_STACK
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mov x3, sp
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mov x2, #CLOBBER_STACK
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1:
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stp x0, x1, [sp, #-16]!
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subs x2, x2, #16
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b.gt 1b
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mov sp, x3
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ret
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stp x0, x1, [sp, #-16]!
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subs x2, x2, #16
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b.gt 1b
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mov sp, x3
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ret
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endfunc
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#define ARG_STACK ((8*(MAX_ARGS - 8) + 15) & ~15)
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function checkasm_checked_call, export=1
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stp x29, x30, [sp, #-16]!
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mov x29, sp
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stp x19, x20, [sp, #-16]!
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stp x21, x22, [sp, #-16]!
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stp x23, x24, [sp, #-16]!
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stp x25, x26, [sp, #-16]!
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stp x27, x28, [sp, #-16]!
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stp d8, d9, [sp, #-16]!
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stp d10, d11, [sp, #-16]!
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stp d12, d13, [sp, #-16]!
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stp d14, d15, [sp, #-16]!
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stp x29, x30, [sp, #-16]!
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mov x29, sp
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stp x19, x20, [sp, #-16]!
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stp x21, x22, [sp, #-16]!
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stp x23, x24, [sp, #-16]!
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stp x25, x26, [sp, #-16]!
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stp x27, x28, [sp, #-16]!
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stp d8, d9, [sp, #-16]!
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stp d10, d11, [sp, #-16]!
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stp d12, d13, [sp, #-16]!
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stp d14, d15, [sp, #-16]!
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movrel x9, register_init
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ldp d8, d9, [x9], #16
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ldp d10, d11, [x9], #16
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ldp d12, d13, [x9], #16
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ldp d14, d15, [x9], #16
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ldp x19, x20, [x9], #16
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ldp x21, x22, [x9], #16
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ldp x23, x24, [x9], #16
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ldp x25, x26, [x9], #16
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ldp x27, x28, [x9], #16
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movrel x9, register_init
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ldp d8, d9, [x9], #16
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ldp d10, d11, [x9], #16
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ldp d12, d13, [x9], #16
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ldp d14, d15, [x9], #16
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ldp x19, x20, [x9], #16
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ldp x21, x22, [x9], #16
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ldp x23, x24, [x9], #16
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ldp x25, x26, [x9], #16
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ldp x27, x28, [x9], #16
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sub sp, sp, #ARG_STACK
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sub sp, sp, #ARG_STACK
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.equ pos, 0
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.rept MAX_ARGS-8
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// Skip the first 8 args, that are loaded into registers
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ldr x9, [x29, #16 + 8*8 + pos]
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str x9, [sp, #pos]
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// Skip the first 8 args, that are loaded into registers
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ldr x9, [x29, #16 + 8*8 + pos]
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str x9, [sp, #pos]
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.equ pos, pos + 8
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.endr
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mov x12, x0
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ldp x0, x1, [x29, #16]
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ldp x2, x3, [x29, #32]
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ldp x4, x5, [x29, #48]
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ldp x6, x7, [x29, #64]
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blr x12
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add sp, sp, #ARG_STACK
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stp x0, x1, [sp, #-16]!
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movrel x9, register_init
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movi v3.8h, #0
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mov x12, x0
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ldp x0, x1, [x29, #16]
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ldp x2, x3, [x29, #32]
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ldp x4, x5, [x29, #48]
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ldp x6, x7, [x29, #64]
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blr x12
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add sp, sp, #ARG_STACK
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stp x0, x1, [sp, #-16]!
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movrel x9, register_init
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movi v3.8h, #0
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.macro check_reg_neon reg1, reg2
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ldr q1, [x9], #16
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uzp1 v2.2d, v\reg1\().2d, v\reg2\().2d
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eor v1.16b, v1.16b, v2.16b
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orr v3.16b, v3.16b, v1.16b
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ldr q1, [x9], #16
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uzp1 v2.2d, v\reg1\().2d, v\reg2\().2d
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eor v1.16b, v1.16b, v2.16b
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orr v3.16b, v3.16b, v1.16b
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.endm
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check_reg_neon 8, 9
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check_reg_neon 10, 11
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check_reg_neon 12, 13
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check_reg_neon 14, 15
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uqxtn v3.8b, v3.8h
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umov x3, v3.d[0]
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check_reg_neon 8, 9
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check_reg_neon 10, 11
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check_reg_neon 12, 13
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check_reg_neon 14, 15
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uqxtn v3.8b, v3.8h
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umov x3, v3.d[0]
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.macro check_reg reg1, reg2
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ldp x0, x1, [x9], #16
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eor x0, x0, \reg1
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eor x1, x1, \reg2
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orr x3, x3, x0
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orr x3, x3, x1
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ldp x0, x1, [x9], #16
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eor x0, x0, \reg1
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eor x1, x1, \reg2
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orr x3, x3, x0
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orr x3, x3, x1
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.endm
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check_reg x19, x20
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check_reg x21, x22
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check_reg x23, x24
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check_reg x25, x26
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check_reg x27, x28
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check_reg x19, x20
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check_reg x21, x22
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check_reg x23, x24
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check_reg x25, x26
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check_reg x27, x28
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cbz x3, 0f
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cbz x3, 0f
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movrel x0, error_message
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bl X(checkasm_fail_func)
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movrel x0, error_message
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bl X(checkasm_fail_func)
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0:
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ldp x0, x1, [sp], #16
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ldp d14, d15, [sp], #16
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ldp d12, d13, [sp], #16
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ldp d10, d11, [sp], #16
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ldp d8, d9, [sp], #16
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ldp x27, x28, [sp], #16
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ldp x25, x26, [sp], #16
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ldp x23, x24, [sp], #16
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ldp x21, x22, [sp], #16
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ldp x19, x20, [sp], #16
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ldp x29, x30, [sp], #16
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ret
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ldp x0, x1, [sp], #16
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ldp d14, d15, [sp], #16
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ldp d12, d13, [sp], #16
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ldp d10, d11, [sp], #16
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ldp d8, d9, [sp], #16
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ldp x27, x28, [sp], #16
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ldp x25, x26, [sp], #16
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ldp x23, x24, [sp], #16
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ldp x21, x22, [sp], #16
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ldp x19, x20, [sp], #16
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ldp x29, x30, [sp], #16
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ret
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endfunc
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@ -29,22 +29,22 @@ ELF .eabi_attribute 10, 0 @ suppress Tag_FP_arch
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#endif
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const register_init, align=3
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.quad 0x21f86d66c8ca00ce
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.quad 0x75b6ba21077c48ad
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.quad 0xed56bb2dcb3c7736
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.quad 0x8bda43d3fd1a7e06
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.quad 0xb64a9c9e5d318408
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.quad 0xdf9a54b303f1d3a3
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.quad 0x4a75479abd64e097
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.quad 0x249214109d5d1c88
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.quad 0x21f86d66c8ca00ce
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.quad 0x75b6ba21077c48ad
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.quad 0xed56bb2dcb3c7736
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.quad 0x8bda43d3fd1a7e06
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.quad 0xb64a9c9e5d318408
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.quad 0xdf9a54b303f1d3a3
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.quad 0x4a75479abd64e097
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.quad 0x249214109d5d1c88
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endconst
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const error_message_fpscr
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.asciz "failed to preserve register FPSCR, changed bits: %x"
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.asciz "failed to preserve register FPSCR, changed bits: %x"
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error_message_gpr:
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.asciz "failed to preserve register r%d"
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.asciz "failed to preserve register r%d"
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error_message_vfp:
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.asciz "failed to preserve register d%d"
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.asciz "failed to preserve register d%d"
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endconst
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@ max number of args used by any asm function.
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@ -58,107 +58,107 @@ endconst
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.macro clobbercheck variant
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.equ pushed, 4*9
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function checkasm_checked_call_\variant, export=1
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push {r4-r11, lr}
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push {r4-r11, lr}
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.ifc \variant, vfp
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vpush {d8-d15}
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fmrx r4, FPSCR
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push {r4}
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vpush {d8-d15}
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fmrx r4, FPSCR
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push {r4}
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.equ pushed, pushed + 16*4 + 4
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.endif
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movrel r12, register_init
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movrel r12, register_init
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.ifc \variant, vfp
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vldm r12, {d8-d15}
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vldm r12, {d8-d15}
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.endif
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ldm r12, {r4-r11}
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ldm r12, {r4-r11}
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sub sp, sp, #ARG_STACK_A
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sub sp, sp, #ARG_STACK_A
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.equ pos, 0
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.rept MAX_ARGS-4
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ldr r12, [sp, #ARG_STACK_A + pushed + 8 + pos]
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str r12, [sp, #pos]
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ldr r12, [sp, #ARG_STACK_A + pushed + 8 + pos]
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str r12, [sp, #pos]
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.equ pos, pos + 4
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.endr
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mov r12, r0
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mov r0, r2
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mov r1, r3
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ldrd r2, r3, [sp, #ARG_STACK_A + pushed]
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blx r12
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add sp, sp, #ARG_STACK_A
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mov r12, r0
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mov r0, r2
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mov r1, r3
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ldrd r2, r3, [sp, #ARG_STACK_A + pushed]
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blx r12
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add sp, sp, #ARG_STACK_A
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push {r0, r1}
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movrel r12, register_init
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push {r0, r1}
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movrel r12, register_init
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.ifc \variant, vfp
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.macro check_reg_vfp, dreg, offset
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ldrd r2, r3, [r12, #8 * (\offset)]
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vmov r0, lr, \dreg
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eor r2, r2, r0
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eor r3, r3, lr
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orrs r2, r2, r3
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bne 4f
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ldrd r2, r3, [r12, #8 * (\offset)]
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vmov r0, lr, \dreg
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eor r2, r2, r0
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eor r3, r3, lr
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orrs r2, r2, r3
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bne 4f
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.endm
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.irp n, 8, 9, 10, 11, 12, 13, 14, 15
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@ keep track of the checked double/SIMD register
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mov r1, #\n
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check_reg_vfp d\n, \n-8
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@ keep track of the checked double/SIMD register
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mov r1, #\n
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check_reg_vfp d\n, \n-8
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.endr
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.purgem check_reg_vfp
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fmrx r1, FPSCR
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ldr r3, [sp, #8]
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eor r1, r1, r3
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@ Ignore changes in bits 0-4 and 7
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bic r1, r1, #0x9f
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@ Ignore changes in the topmost 5 bits
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bics r1, r1, #0xf8000000
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bne 3f
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fmrx r1, FPSCR
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ldr r3, [sp, #8]
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eor r1, r1, r3
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@ Ignore changes in bits 0-4 and 7
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bic r1, r1, #0x9f
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@ Ignore changes in the topmost 5 bits
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bics r1, r1, #0xf8000000
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bne 3f
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.endif
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@ keep track of the checked GPR
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mov r1, #4
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@ keep track of the checked GPR
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mov r1, #4
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.macro check_reg reg1, reg2=
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ldrd r2, r3, [r12], #8
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eors r2, r2, \reg1
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bne 2f
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add r1, r1, #1
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ldrd r2, r3, [r12], #8
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eors r2, r2, \reg1
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bne 2f
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add r1, r1, #1
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.ifnb \reg2
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eors r3, r3, \reg2
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bne 2f
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eors r3, r3, \reg2
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bne 2f
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.endif
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add r1, r1, #1
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add r1, r1, #1
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.endm
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check_reg r4, r5
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check_reg r6, r7
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check_reg r4, r5
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check_reg r6, r7
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@ r9 is a volatile register in the ios ABI
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#ifdef __APPLE__
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check_reg r8
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check_reg r8
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#else
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check_reg r8, r9
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check_reg r8, r9
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#endif
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check_reg r10, r11
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check_reg r10, r11
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.purgem check_reg
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b 0f
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b 0f
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4:
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movrel r0, error_message_vfp
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b 1f
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movrel r0, error_message_vfp
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b 1f
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3:
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movrel r0, error_message_fpscr
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b 1f
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movrel r0, error_message_fpscr
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b 1f
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2:
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movrel r0, error_message_gpr
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movrel r0, error_message_gpr
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1:
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blx X(checkasm_fail_func)
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blx X(checkasm_fail_func)
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0:
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pop {r0, r1}
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pop {r0, r1}
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.ifc \variant, vfp
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pop {r2}
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fmxr FPSCR, r2
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vpop {d8-d15}
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pop {r2}
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fmxr FPSCR, r2
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vpop {d8-d15}
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.endif
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pop {r4-r11, pc}
|
||||
pop {r4-r11, pc}
|
||||
endfunc
|
||||
.endm
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user