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Merge remote-tracking branch 'qatar/master'

Browse Source 
* qatar/master:
  sparc: Eliminate dead code in VIS acceleration macros
  flacdec: drop unnecessary assert
  mjpegdec: properly report unsupported disabled features

Conflicts:
	libavcodec/flacdec.c
	libavcodec/mjpegdec.c

Merged-by: Michael Niedermayer <michaelni@gmx.at>
This commit is contained in:
Michael Niedermayer 2013-05-16 17:10:51 +02:00
commit c607a2cc97
2 changed files with 7 additions and 58 deletions
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7
libavcodec/mjpegdec.c
View File

@ -1682,6 +1682,13 @@ int ff_mjpeg_decode_frame(AVCodecContext *avctx, void *data, int *got_frame,
mjpeg_decode_com(s);
ret = -1;
if (!CONFIG_JPEGLS_DECODER &&
(start_code == SOF48 || start_code == LSE)) {
av_log(avctx, AV_LOG_ERROR, "JPEG-LS support not enabled.\n");
return AVERROR(ENOSYS);
}
switch (start_code) {
case SOI:
s->restart_interval = 0;

58
libavcodec/sparc/vis.h
View File

@ -173,32 +173,6 @@ static inline void vis_set_gsr(unsigned int _val)
#define vis_st64(rs1,mem) vis_r2m(std, rs1, mem)
#define vis_st64_2(rs1,mem1,mem2) vis_r2m_2(std, rs1, mem1, mem2)
#define vis_ldblk(mem, rd) \
do { register void *__mem __asm__("g1"); \
__mem = &(mem); \
__asm__ volatile(".word 0xc1985e00 | %1" \
: \
: "r" (__mem), \
"i" (vis_rd_d(rd)) \
: "memory"); \
} while (0)
#define vis_stblk(rd, mem) \
do { register void *__mem __asm__("g1"); \
__mem = &(mem); \
__asm__ volatile(".word 0xc1b85e00 | %1" \
: \
: "r" (__mem), \
"i" (vis_rd_d(rd)) \
: "memory"); \
} while (0)
#define vis_membar_storestore() \
__asm__ volatile(".word 0x8143e008" : : : "memory")
#define vis_membar_sync() \
__asm__ volatile(".word 0x8143e040" : : : "memory")
/* 16 and 32 bit partitioned addition and subtraction. The normal
* versions perform 4 16-bit or 2 32-bit additions or subtractions.
* The 's' versions perform 2 16-bit or 1 32-bit additions or
@ -266,38 +240,6 @@ static inline void vis_alignaddr_g0(void *_ptr)
vis_rd_s(0)));
}
static inline void *vis_alignaddrl(void *_ptr)
{
register void *ptr __asm__("g1");
ptr = _ptr;
__asm__ volatile(".word %2"
: "=&r" (ptr)
: "0" (ptr),
"i" (vis_opc_base | vis_opf(0x19) |
vis_rs1_s(1) |
vis_rs2_s(0) |
vis_rd_s(1)));
return ptr;
}
static inline void vis_alignaddrl_g0(void *_ptr)
{
register void *ptr __asm__("g1");
ptr = _ptr;
__asm__ volatile(".word %2"
: "=&r" (ptr)
: "0" (ptr),
"i" (vis_opc_base | vis_opf(0x19) |
vis_rs1_s(1) |
vis_rs2_s(0) |
vis_rd_s(0)));
}
#define vis_faligndata(rs1,rs2,rd) vis_dd2d(0x48, rs1, rs2, rd)
/* Logical operate instructions. */