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616fdeaea3
There is no known (real) hardware with V and without the complete B extension. B was indeed required in the RISC-V application profile from 2022, earlier than V. There should not be any relevant hardware in the future either. In practice, different R-V Vector optimisations in FFmpeg already depend on every constituent of the B extension anyhow, so it would not work well.
60 lines
2.1 KiB
C
60 lines
2.1 KiB
C
/*
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* Copyright (c) 2024 Rémi Denis-Courmont.
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "config.h"
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#include "libavutil/attributes.h"
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#include "libavutil/cpu.h"
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#include "libavutil/riscv/cpu.h"
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#include "libavcodec/vp8dsp.h"
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void ff_vp7_luma_dc_wht_rvv(int16_t block[4][4][16], int16_t dc[16]);
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void ff_vp7_idct_add_rvv(uint8_t *dst, int16_t block[16], ptrdiff_t stride);
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void ff_vp78_idct_dc_add_rvv(uint8_t *, int16_t block[16], ptrdiff_t, int dc);
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void ff_vp7_idct_dc_add4y_rvv(uint8_t *dst, int16_t block[4][16], ptrdiff_t);
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void ff_vp7_idct_dc_add4uv_rvv(uint8_t *dst, int16_t block[4][16], ptrdiff_t);
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static void ff_vp7_idct_dc_add_rvv(uint8_t *dst, int16_t block[16],
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ptrdiff_t stride)
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{
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int dc = (23170 * (23170 * block[0] >> 14) + 0x20000) >> 18;
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ff_vp78_idct_dc_add_rvv(dst, block, stride, dc);
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}
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av_cold void ff_vp7dsp_init_riscv(VP8DSPContext *c)
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{
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#if HAVE_RVV
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int flags = av_get_cpu_flags();
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if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB) &&
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ff_rv_vlen_least(128)) {
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#if __riscv_xlen >= 64
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c->vp8_luma_dc_wht = ff_vp7_luma_dc_wht_rvv;
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c->vp8_idct_add = ff_vp7_idct_add_rvv;
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#endif
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c->vp8_idct_dc_add = ff_vp7_idct_dc_add_rvv;
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c->vp8_idct_dc_add4y = ff_vp7_idct_dc_add4y_rvv;
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if (flags & AV_CPU_FLAG_RVV_I64)
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c->vp8_idct_dc_add4uv = ff_vp7_idct_dc_add4uv_rvv;
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}
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#endif
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}
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