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https://git.ffmpeg.org/ffmpeg.git
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3602ad7ee6
* commit '142e76f1055de5dde44696e71a5f63f2cb11dedf': swscale: fix crash with dithering due incorrect offset calculation. matroskadec: fix stupid typo (!= -> ==) build: remove duplicates from order-only directory prerequisite list build: rework rules for things in the tools dir configure: fix --cpu=host with gcc 4.6 ARM: use const macro to define constant data in asm bitdepth: simplify FUNC/FUNCC macros dsputil: remove ff_emulated_edge_mc macro used in one place 9/10-bit: simplify clipping macros matroskadec: reindent matroskadec: defer parsing of cues element until we seek. lavc: add support for codec-specific defaults. lavc: make avcodec_alloc_context3 officially public. lavc: remove a half-working attempt at different defaults for audio/video codecs. ac3dec: add a drc_scale private option lavf: add avformat_find_stream_info() lavc: introduce avcodec_open2() as a replacement for avcodec_open(). Conflicts: Makefile libavcodec/utils.c libavformat/avformat.h libswscale/swscale_internal.h Merged-by: Michael Niedermayer <michaelni@gmx.at>
360 lines
12 KiB
ArmAsm
360 lines
12 KiB
ArmAsm
/*
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* Copyright (c) 2009 Mans Rullgard <mans@mansr.com>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "asm.S"
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.macro ldcol.8 rd, rs, rt, n=8, hi=0
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.if \n == 8 || \hi == 0
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vld1.8 {\rd[0]}, [\rs], \rt
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vld1.8 {\rd[1]}, [\rs], \rt
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vld1.8 {\rd[2]}, [\rs], \rt
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vld1.8 {\rd[3]}, [\rs], \rt
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.endif
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.if \n == 8 || \hi == 1
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vld1.8 {\rd[4]}, [\rs], \rt
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vld1.8 {\rd[5]}, [\rs], \rt
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vld1.8 {\rd[6]}, [\rs], \rt
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vld1.8 {\rd[7]}, [\rs], \rt
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.endif
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.endm
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.macro add16x8 dq, dl, dh, rl, rh
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vaddl.u8 \dq, \rl, \rh
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vadd.u16 \dl, \dl, \dh
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vpadd.u16 \dl, \dl, \dl
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vpadd.u16 \dl, \dl, \dl
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.endm
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function ff_pred16x16_128_dc_neon, export=1
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vmov.i8 q0, #128
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b .L_pred16x16_dc_end
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endfunc
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function ff_pred16x16_top_dc_neon, export=1
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sub r2, r0, r1
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vld1.8 {q0}, [r2,:128]
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add16x8 q0, d0, d1, d0, d1
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vrshrn.u16 d0, q0, #4
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vdup.8 q0, d0[0]
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b .L_pred16x16_dc_end
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endfunc
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function ff_pred16x16_left_dc_neon, export=1
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sub r2, r0, #1
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ldcol.8 d0, r2, r1
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ldcol.8 d1, r2, r1
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add16x8 q0, d0, d1, d0, d1
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vrshrn.u16 d0, q0, #4
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vdup.8 q0, d0[0]
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b .L_pred16x16_dc_end
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endfunc
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function ff_pred16x16_dc_neon, export=1
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sub r2, r0, r1
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vld1.8 {q0}, [r2,:128]
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sub r2, r0, #1
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ldcol.8 d2, r2, r1
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ldcol.8 d3, r2, r1
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vaddl.u8 q0, d0, d1
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vaddl.u8 q1, d2, d3
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vadd.u16 q0, q0, q1
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vadd.u16 d0, d0, d1
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vpadd.u16 d0, d0, d0
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vpadd.u16 d0, d0, d0
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vrshrn.u16 d0, q0, #5
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vdup.8 q0, d0[0]
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.L_pred16x16_dc_end:
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mov r3, #8
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6: vst1.8 {q0}, [r0,:128], r1
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vst1.8 {q0}, [r0,:128], r1
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subs r3, r3, #1
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bne 6b
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bx lr
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endfunc
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function ff_pred16x16_hor_neon, export=1
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sub r2, r0, #1
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mov r3, #16
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1: vld1.8 {d0[],d1[]},[r2], r1
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vst1.8 {q0}, [r0,:128], r1
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subs r3, r3, #1
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bne 1b
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bx lr
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endfunc
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function ff_pred16x16_vert_neon, export=1
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sub r0, r0, r1
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vld1.8 {q0}, [r0,:128], r1
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mov r3, #8
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1: vst1.8 {q0}, [r0,:128], r1
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vst1.8 {q0}, [r0,:128], r1
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subs r3, r3, #1
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bne 1b
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bx lr
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endfunc
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function ff_pred16x16_plane_neon, export=1
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sub r3, r0, r1
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add r2, r3, #8
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sub r3, r3, #1
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vld1.8 {d0}, [r3]
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vld1.8 {d2}, [r2,:64], r1
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ldcol.8 d1, r3, r1
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add r3, r3, r1
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ldcol.8 d3, r3, r1
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vrev64.8 q0, q0
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vaddl.u8 q8, d2, d3
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vsubl.u8 q2, d2, d0
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vsubl.u8 q3, d3, d1
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movrel r3, p16weight
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vld1.8 {q0}, [r3,:128]
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vmul.s16 q2, q2, q0
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vmul.s16 q3, q3, q0
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vadd.i16 d4, d4, d5
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vadd.i16 d5, d6, d7
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vpadd.i16 d4, d4, d5
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vpadd.i16 d4, d4, d4
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vshll.s16 q3, d4, #2
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vaddw.s16 q2, q3, d4
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vrshrn.s32 d4, q2, #6
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mov r3, #0
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vtrn.16 d4, d5
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vadd.i16 d2, d4, d5
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vshl.i16 d3, d2, #3
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vrev64.16 d16, d17
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vsub.i16 d3, d3, d2
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vadd.i16 d16, d16, d0
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vshl.i16 d2, d16, #4
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vsub.i16 d2, d2, d3
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vshl.i16 d3, d4, #4
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vext.16 q0, q0, q0, #7
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vsub.i16 d6, d5, d3
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vmov.16 d0[0], r3
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vmul.i16 q0, q0, d4[0]
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vdup.16 q1, d2[0]
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vdup.16 q2, d4[0]
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vdup.16 q3, d6[0]
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vshl.i16 q2, q2, #3
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vadd.i16 q1, q1, q0
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vadd.i16 q3, q3, q2
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mov r3, #16
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1:
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vqshrun.s16 d0, q1, #5
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vadd.i16 q1, q1, q2
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vqshrun.s16 d1, q1, #5
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vadd.i16 q1, q1, q3
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vst1.8 {q0}, [r0,:128], r1
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subs r3, r3, #1
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bne 1b
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bx lr
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endfunc
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const p16weight, align=4
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.short 1,2,3,4,5,6,7,8
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endconst
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function ff_pred8x8_hor_neon, export=1
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sub r2, r0, #1
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mov r3, #8
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1: vld1.8 {d0[]}, [r2], r1
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vst1.8 {d0}, [r0,:64], r1
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subs r3, r3, #1
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bne 1b
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bx lr
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endfunc
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function ff_pred8x8_vert_neon, export=1
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sub r0, r0, r1
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vld1.8 {d0}, [r0,:64], r1
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mov r3, #4
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1: vst1.8 {d0}, [r0,:64], r1
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vst1.8 {d0}, [r0,:64], r1
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subs r3, r3, #1
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bne 1b
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bx lr
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endfunc
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function ff_pred8x8_plane_neon, export=1
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sub r3, r0, r1
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add r2, r3, #4
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sub r3, r3, #1
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vld1.32 {d0[0]}, [r3]
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vld1.32 {d2[0]}, [r2,:32], r1
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ldcol.8 d0, r3, r1, 4, hi=1
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add r3, r3, r1
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ldcol.8 d3, r3, r1, 4
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vaddl.u8 q8, d2, d3
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vrev32.8 d0, d0
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vtrn.32 d2, d3
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vsubl.u8 q2, d2, d0
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movrel r3, p16weight
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vld1.16 {q0}, [r3,:128]
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vmul.s16 d4, d4, d0
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vmul.s16 d5, d5, d0
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vpadd.i16 d4, d4, d5
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vpaddl.s16 d4, d4
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vshl.i32 d5, d4, #4
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vadd.s32 d4, d4, d5
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vrshrn.s32 d4, q2, #5
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mov r3, #0
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vtrn.16 d4, d5
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vadd.i16 d2, d4, d5
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vshl.i16 d3, d2, #2
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vrev64.16 d16, d16
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vsub.i16 d3, d3, d2
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vadd.i16 d16, d16, d0
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vshl.i16 d2, d16, #4
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vsub.i16 d2, d2, d3
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vshl.i16 d3, d4, #3
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vext.16 q0, q0, q0, #7
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vsub.i16 d6, d5, d3
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vmov.16 d0[0], r3
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vmul.i16 q0, q0, d4[0]
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vdup.16 q1, d2[0]
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vdup.16 q2, d4[0]
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vdup.16 q3, d6[0]
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vshl.i16 q2, q2, #3
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vadd.i16 q1, q1, q0
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vadd.i16 q3, q3, q2
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mov r3, #8
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1:
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vqshrun.s16 d0, q1, #5
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vadd.i16 q1, q1, q3
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vst1.8 {d0}, [r0,:64], r1
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subs r3, r3, #1
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bne 1b
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bx lr
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endfunc
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function ff_pred8x8_128_dc_neon, export=1
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vmov.i8 q0, #128
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b .L_pred8x8_dc_end
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endfunc
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function ff_pred8x8_top_dc_neon, export=1
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sub r2, r0, r1
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vld1.8 {d0}, [r2,:64]
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vpaddl.u8 d0, d0
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vpadd.u16 d0, d0, d0
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vrshrn.u16 d0, q0, #2
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vdup.8 d1, d0[1]
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vdup.8 d0, d0[0]
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vtrn.32 d0, d1
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b .L_pred8x8_dc_end
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endfunc
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function ff_pred8x8_left_dc_neon, export=1
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sub r2, r0, #1
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ldcol.8 d0, r2, r1
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vpaddl.u8 d0, d0
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vpadd.u16 d0, d0, d0
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vrshrn.u16 d0, q0, #2
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vdup.8 d1, d0[1]
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vdup.8 d0, d0[0]
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b .L_pred8x8_dc_end
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endfunc
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function ff_pred8x8_dc_neon, export=1
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sub r2, r0, r1
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vld1.8 {d0}, [r2,:64]
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sub r2, r0, #1
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ldcol.8 d1, r2, r1
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vtrn.32 d0, d1
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vpaddl.u8 q0, q0
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vpadd.u16 d0, d0, d1
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vpadd.u16 d1, d0, d0
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vrshrn.u16 d2, q0, #3
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vrshrn.u16 d3, q0, #2
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vdup.8 d0, d2[4]
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vdup.8 d1, d3[3]
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vdup.8 d4, d3[2]
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vdup.8 d5, d2[5]
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vtrn.32 q0, q2
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.L_pred8x8_dc_end:
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mov r3, #4
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add r2, r0, r1, lsl #2
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6: vst1.8 {d0}, [r0,:64], r1
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vst1.8 {d1}, [r2,:64], r1
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subs r3, r3, #1
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bne 6b
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bx lr
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endfunc
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function ff_pred8x8_l0t_dc_neon, export=1
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sub r2, r0, r1
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vld1.8 {d0}, [r2,:64]
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sub r2, r0, #1
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ldcol.8 d1, r2, r1, 4
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vtrn.32 d0, d1
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vpaddl.u8 q0, q0
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vpadd.u16 d0, d0, d1
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vpadd.u16 d1, d0, d0
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vrshrn.u16 d2, q0, #3
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vrshrn.u16 d3, q0, #2
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vdup.8 d0, d2[4]
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vdup.8 d1, d3[0]
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vdup.8 q2, d3[2]
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vtrn.32 q0, q2
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b .L_pred8x8_dc_end
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endfunc
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function ff_pred8x8_l00_dc_neon, export=1
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sub r2, r0, #1
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ldcol.8 d0, r2, r1, 4
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vpaddl.u8 d0, d0
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vpadd.u16 d0, d0, d0
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vrshrn.u16 d0, q0, #2
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vmov.i8 d1, #128
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vdup.8 d0, d0[0]
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b .L_pred8x8_dc_end
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endfunc
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function ff_pred8x8_0lt_dc_neon, export=1
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sub r2, r0, r1
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vld1.8 {d0}, [r2,:64]
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add r2, r0, r1, lsl #2
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sub r2, r2, #1
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ldcol.8 d1, r2, r1, 4, hi=1
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vtrn.32 d0, d1
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vpaddl.u8 q0, q0
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vpadd.u16 d0, d0, d1
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vpadd.u16 d1, d0, d0
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vrshrn.u16 d3, q0, #2
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vrshrn.u16 d2, q0, #3
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vdup.8 d0, d3[0]
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vdup.8 d1, d3[3]
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vdup.8 d4, d3[2]
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vdup.8 d5, d2[5]
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vtrn.32 q0, q2
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b .L_pred8x8_dc_end
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endfunc
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function ff_pred8x8_0l0_dc_neon, export=1
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add r2, r0, r1, lsl #2
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sub r2, r2, #1
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ldcol.8 d1, r2, r1, 4
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vpaddl.u8 d2, d1
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vpadd.u16 d2, d2, d2
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vrshrn.u16 d1, q1, #2
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vmov.i8 d0, #128
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vdup.8 d1, d1[0]
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b .L_pred8x8_dc_end
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endfunc
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