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https://git.ffmpeg.org/ffmpeg.git
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bbe95f7353
From x86inc: > On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either > a branch or a branch target. So switch to a 2-byte form of ret in that case. > We can automatically detect "follows a branch", but not a branch target. > (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.) x86inc can automatically determine whether to use REP_RET rather than REP in most of these cases, so impact is minimal. Additionally, a few REP_RETs were used unnecessary, despite the return being nowhere near a branch. The only CPUs affected were AMD K10s, made between 2007 and 2011, 16 years ago and 12 years ago, respectively. In the future, everyone involved with x86inc should consider dropping REP_RETs altogether.
135 lines
4.2 KiB
NASM
135 lines
4.2 KiB
NASM
;******************************************************************************
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;* x86-optimized yuv2yuvX
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;* Copyright 2020 Google LLC
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;* Copyright (C) 2001-2011 Michael Niedermayer <michaelni@gmx.at>
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "libavutil/x86/x86util.asm"
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SECTION .text
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;-----------------------------------------------------------------------------
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; yuv2yuvX
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;
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; void ff_yuv2yuvX_<opt>(const int16_t *filter, int filterSize,
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; int srcOffset, uint8_t *dest, int dstW,
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; const uint8_t *dither, int offset);
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;
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;-----------------------------------------------------------------------------
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%macro YUV2YUVX_FUNC 0
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cglobal yuv2yuvX, 7, 7, 8, filter, filterSize, src, dest, dstW, dither, offset
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%if notcpuflag(sse3)
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%define movr mova
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%define unroll 1
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%else
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%define movr movdqu
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%define unroll 2
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%endif
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movsxdifnidn dstWq, dstWd
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movsxdifnidn offsetq, offsetd
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movsxdifnidn srcq, srcd
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%if cpuflag(avx2)
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vpbroadcastq m3, [ditherq]
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%else
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movq xm3, [ditherq]
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%endif ; avx2
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cmp offsetd, 0
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jz .offset
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; offset != 0 path.
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psrlq m5, m3, $18
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psllq m3, m3, $28
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por m3, m3, m5
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.offset:
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add offsetq, srcq
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movd xm1, filterSized
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SPLATW m1, xm1, 0
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pxor m0, m0, m0
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mov filterSizeq, filterq
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mov srcq, [filterSizeq]
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punpcklbw m3, m0
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psllw m1, m1, 3
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paddw m3, m3, m1
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psraw m7, m3, 4
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.outerloop:
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mova m4, m7
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mova m3, m7
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%if cpuflag(sse3)
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mova m6, m7
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mova m1, m7
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%endif
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.loop:
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%if cpuflag(avx2)
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vpbroadcastq m0, [filterSizeq + 8]
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%elif cpuflag(sse3)
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movddup m0, [filterSizeq + 8]
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%else
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mova m0, [filterSizeq + 8]
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%endif
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pmulhw m2, m0, [srcq + offsetq * 2]
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pmulhw m5, m0, [srcq + offsetq * 2 + mmsize]
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paddw m3, m3, m2
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paddw m4, m4, m5
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%if cpuflag(sse3)
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pmulhw m2, m0, [srcq + offsetq * 2 + 2 * mmsize]
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pmulhw m5, m0, [srcq + offsetq * 2 + 3 * mmsize]
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paddw m6, m6, m2
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paddw m1, m1, m5
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%endif
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add filterSizeq, $10
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mov srcq, [filterSizeq]
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test srcq, srcq
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jnz .loop
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psraw m3, m3, 3
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psraw m4, m4, 3
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%if cpuflag(sse3)
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psraw m6, m6, 3
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psraw m1, m1, 3
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%endif
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packuswb m3, m3, m4
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%if cpuflag(sse3)
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packuswb m6, m6, m1
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%endif
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mov srcq, [filterq]
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%if cpuflag(avx2)
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vpermq m3, m3, 216
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vpermq m6, m6, 216
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%endif
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movr [destq + offsetq], m3
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%if cpuflag(sse3)
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movr [destq + offsetq + mmsize], m6
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%endif
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add offsetq, mmsize * unroll
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mov filterSizeq, filterq
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cmp offsetq, dstWq
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jb .outerloop
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RET
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%endmacro
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INIT_MMX mmxext
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YUV2YUVX_FUNC
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INIT_XMM sse3
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YUV2YUVX_FUNC
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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YUV2YUVX_FUNC
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%endif
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