mirror of
https://git.ffmpeg.org/ffmpeg.git
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bbe95f7353
From x86inc: > On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either > a branch or a branch target. So switch to a 2-byte form of ret in that case. > We can automatically detect "follows a branch", but not a branch target. > (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.) x86inc can automatically determine whether to use REP_RET rather than REP in most of these cases, so impact is minimal. Additionally, a few REP_RETs were used unnecessary, despite the return being nowhere near a branch. The only CPUs affected were AMD K10s, made between 2007 and 2011, 16 years ago and 12 years ago, respectively. In the future, everyone involved with x86inc should consider dropping REP_RETs altogether.
186 lines
5.6 KiB
NASM
186 lines
5.6 KiB
NASM
;************************************************************************
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;* SIMD-optimized lossless video encoding functions
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;* Copyright (c) 2000, 2001 Fabrice Bellard
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;* Copyright (c) 2002-2004 Michael Niedermayer <michaelni@gmx.at>
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;*
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;* MMX optimization by Nick Kurshev <nickols_k@mail.ru>
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;* Conversion to NASM format by Tiancheng "Timothy" Gu <timothygu99@gmail.com>
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* 51, Inc., Foundation Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "libavutil/x86/x86util.asm"
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cextern pb_80
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SECTION .text
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; void ff_diff_bytes(uint8_t *dst, const uint8_t *src1, const uint8_t *src2,
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; intptr_t w);
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%macro DIFF_BYTES_PROLOGUE 0
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%if ARCH_X86_32
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cglobal diff_bytes, 3,5,2, dst, src1, src2
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%define wq r4q
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DECLARE_REG_TMP 3
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mov wq, r3mp
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%else
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cglobal diff_bytes, 4,5,2, dst, src1, src2, w
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DECLARE_REG_TMP 4
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%endif ; ARCH_X86_32
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%define i t0q
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%endmacro
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; labels to jump to if w < regsize and w < 0
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%macro DIFF_BYTES_LOOP_PREP 2
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mov i, wq
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and i, -2 * regsize
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js %2
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jz %1
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add dstq, i
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add src1q, i
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add src2q, i
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neg i
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%endmacro
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; mov type used for src1q, dstq, first reg, second reg
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%macro DIFF_BYTES_LOOP_CORE 4
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%if mmsize != 16
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mov%1 %3, [src1q + i]
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mov%1 %4, [src1q + i + regsize]
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psubb %3, [src2q + i]
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psubb %4, [src2q + i + regsize]
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mov%2 [dstq + i], %3
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mov%2 [regsize + dstq + i], %4
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%else
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; SSE enforces alignment of psubb operand
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mov%1 %3, [src1q + i]
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movu %4, [src2q + i]
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psubb %3, %4
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mov%2 [dstq + i], %3
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mov%1 %3, [src1q + i + regsize]
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movu %4, [src2q + i + regsize]
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psubb %3, %4
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mov%2 [regsize + dstq + i], %3
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%endif
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%endmacro
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%macro DIFF_BYTES_BODY 2 ; mov type used for src1q, for dstq
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%define regsize mmsize
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.loop_%1%2:
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DIFF_BYTES_LOOP_CORE %1, %2, m0, m1
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add i, 2 * regsize
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jl .loop_%1%2
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.skip_main_%1%2:
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and wq, 2 * regsize - 1
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jz .end_%1%2
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%if mmsize > 16
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; fall back to narrower xmm
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%define regsize (mmsize / 2)
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DIFF_BYTES_LOOP_PREP .setup_loop_gpr_aa, .end_aa
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.loop2_%1%2:
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DIFF_BYTES_LOOP_CORE %1, %2, xm0, xm1
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add i, 2 * regsize
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jl .loop2_%1%2
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.setup_loop_gpr_%1%2:
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and wq, 2 * regsize - 1
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jz .end_%1%2
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%endif
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add dstq, wq
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add src1q, wq
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add src2q, wq
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neg wq
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.loop_gpr_%1%2:
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mov t0b, [src1q + wq]
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sub t0b, [src2q + wq]
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mov [dstq + wq], t0b
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inc wq
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jl .loop_gpr_%1%2
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.end_%1%2:
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RET
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%endmacro
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INIT_XMM sse2
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DIFF_BYTES_PROLOGUE
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%define regsize mmsize
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DIFF_BYTES_LOOP_PREP .skip_main_aa, .end_aa
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test dstq, regsize - 1
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jnz .loop_uu
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test src1q, regsize - 1
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jnz .loop_ua
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DIFF_BYTES_BODY a, a
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DIFF_BYTES_BODY u, a
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DIFF_BYTES_BODY u, u
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%undef i
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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DIFF_BYTES_PROLOGUE
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%define regsize mmsize
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; Directly using unaligned SSE2 version is marginally faster than
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; branching based on arguments.
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DIFF_BYTES_LOOP_PREP .skip_main_uu, .end_uu
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test dstq, regsize - 1
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jnz .loop_uu
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test src1q, regsize - 1
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jnz .loop_ua
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DIFF_BYTES_BODY a, a
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DIFF_BYTES_BODY u, a
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DIFF_BYTES_BODY u, u
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%undef i
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%endif
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;--------------------------------------------------------------------------------------------------
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;void sub_left_predict(uint8_t *dst, const uint8_t *src, ptrdiff_t stride, ptrdiff_t width, int height)
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;--------------------------------------------------------------------------------------------------
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INIT_XMM avx
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cglobal sub_left_predict, 5,6,5, dst, src, stride, width, height, x
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mova m1, [pb_80] ; prev initial
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add dstq, widthq
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add srcq, widthq
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lea xd, [widthq-1]
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neg widthq
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and xd, 15
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pinsrb m4, m1, xd, 15
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mov xq, widthq
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.loop:
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movu m0, [srcq + widthq]
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palignr m2, m0, m1, 15
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movu m1, [srcq + widthq + 16]
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palignr m3, m1, m0, 15
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psubb m2, m0, m2
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psubb m3, m1, m3
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movu [dstq + widthq], m2
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movu [dstq + widthq + 16], m3
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add widthq, 2 * 16
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jl .loop
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add srcq, strideq
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sub dstq, xq ; dst + width
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test xd, 16
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jz .mod32
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mova m1, m0
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.mod32:
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pshufb m1, m4
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mov widthq, xq
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dec heightd
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jg .loop
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RET
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