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d808070547
This uses the architected RISC-V 64-bit cycle counter from the RISC-V unprivileged instruction set. In 64-bit and 128-bit, this is a straightforward CSR read. In 32-bit mode, the 64-bit value is exposed as two CSRs, which cannot be read atomically, so a loop is necessary to detect and fix up the race condition where the bottom half wraps exactly between the two reads.
54 lines
1.4 KiB
C
54 lines
1.4 KiB
C
/*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef AVUTIL_RISCV_TIMER_H
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#define AVUTIL_RISCV_TIMER_H
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#include "config.h"
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#if HAVE_INLINE_ASM
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#include <stdint.h>
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static inline uint64_t rdcycle64(void)
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{
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#if (__riscv_xlen >= 64)
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uintptr_t cycles;
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__asm__ volatile ("rdcycle %0" : "=r"(cycles));
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#else
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uint64_t cycles;
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uint32_t hi, lo, check;
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__asm__ volatile (
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"1: rdcycleh %0\n"
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" rdcycle %1\n"
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" rdcycleh %2\n"
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" bne %0, %2, 1b\n" : "=r" (hi), "=r" (lo), "=r" (check));
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cycles = (((uint64_t)hi) << 32) | lo;
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#endif
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return cycles;
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}
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#define AV_READ_TIME rdcycle64
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#endif
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#endif /* AVUTIL_RISCV_TIMER_H */
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