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https://git.ffmpeg.org/ffmpeg.git
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bbe95f7353
From x86inc: > On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either > a branch or a branch target. So switch to a 2-byte form of ret in that case. > We can automatically detect "follows a branch", but not a branch target. > (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.) x86inc can automatically determine whether to use REP_RET rather than REP in most of these cases, so impact is minimal. Additionally, a few REP_RETs were used unnecessary, despite the return being nowhere near a branch. The only CPUs affected were AMD K10s, made between 2007 and 2011, 16 years ago and 12 years ago, respectively. In the future, everyone involved with x86inc should consider dropping REP_RETs altogether.
170 lines
5.1 KiB
NASM
170 lines
5.1 KiB
NASM
;******************************************************************************
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;* MMX/SSE2-optimized functions for the RV30 and RV40 decoders
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;* Copyright (C) 2012 Christophe Gisquet <christophe.gisquet@gmail.com>
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "libavutil/x86/x86util.asm"
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SECTION_RODATA
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pw_row_coeffs: times 4 dw 13
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times 4 dw 17
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times 4 dw 7
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pd_512: times 2 dd 0x200
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pw_col_coeffs: dw 13, 13, 13, -13
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dw 17, 7, 7, -17
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dw 13, -13, 13, 13
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dw -7, 17, -17, -7
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SECTION .text
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%macro IDCT_DC_NOROUND 1
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imul %1, 13*13*3
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sar %1, 11
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%endmacro
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%macro IDCT_DC_ROUND 1
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imul %1, 13*13
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add %1, 0x200
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sar %1, 10
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%endmacro
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INIT_MMX mmxext
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cglobal rv34_idct_dc_noround, 1, 2, 0
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movsx r1, word [r0]
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IDCT_DC_NOROUND r1
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movd m0, r1d
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pshufw m0, m0, 0
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movq [r0+ 0], m0
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movq [r0+ 8], m0
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movq [r0+16], m0
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movq [r0+24], m0
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RET
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; Load coeffs and perform row transform
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; Output: coeffs in mm[0467], rounder in mm5
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%macro ROW_TRANSFORM 1
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pxor mm7, mm7
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mova mm0, [%1+ 0*8]
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mova mm1, [%1+ 1*8]
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mova mm2, [%1+ 2*8]
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mova mm3, [%1+ 3*8]
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mova [%1+ 0*8], mm7
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mova [%1+ 1*8], mm7
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mova [%1+ 2*8], mm7
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mova [%1+ 3*8], mm7
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mova mm4, mm0
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mova mm6, [pw_row_coeffs+ 0]
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paddsw mm0, mm2 ; b0 + b2
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psubsw mm4, mm2 ; b0 - b2
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pmullw mm0, mm6 ; *13 = z0
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pmullw mm4, mm6 ; *13 = z1
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mova mm5, mm1
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pmullw mm1, [pw_row_coeffs+ 8] ; b1*17
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pmullw mm5, [pw_row_coeffs+16] ; b1* 7
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mova mm7, mm3
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pmullw mm3, [pw_row_coeffs+ 8] ; b3*17
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pmullw mm7, [pw_row_coeffs+16] ; b3* 7
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paddsw mm1, mm7 ; z3 = b1*17 + b3* 7
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psubsw mm5, mm3 ; z2 = b1* 7 - b3*17
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mova mm7, mm0
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mova mm6, mm4
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paddsw mm0, mm1 ; z0 + z3
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psubsw mm7, mm1 ; z0 - z3
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paddsw mm4, mm5 ; z1 + z2
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psubsw mm6, mm5 ; z1 - z2
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mova mm5, [pd_512] ; 0x200
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%endmacro
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; ff_rv34_idct_add_mmxext(uint8_t *dst, ptrdiff_t stride, int16_t *block);
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%macro COL_TRANSFORM 4
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pshufw mm3, %2, 0xDD ; col. 1,3,1,3
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pshufw %2, %2, 0x88 ; col. 0,2,0,2
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pmaddwd %2, %3 ; 13*c0+13*c2 | 13*c0-13*c2 = z0 | z1
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pmaddwd mm3, %4 ; 17*c1+ 7*c3 | 7*c1-17*c3 = z3 | z2
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paddd %2, mm5
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pshufw mm1, %2, 01001110b ; z1 | z0
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pshufw mm2, mm3, 01001110b ; z2 | z3
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paddd %2, mm3 ; z0+z3 | z1+z2
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psubd mm1, mm2 ; z1-z2 | z0-z3
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movd mm3, %1
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psrad %2, 10
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pxor mm2, mm2
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psrad mm1, 10
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punpcklbw mm3, mm2
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packssdw %2, mm1
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paddw %2, mm3
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packuswb %2, %2
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movd %1, %2
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%endmacro
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INIT_MMX mmxext
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cglobal rv34_idct_add, 3,3,0, d, s, b
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ROW_TRANSFORM bq
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COL_TRANSFORM [dq], mm0, [pw_col_coeffs+ 0], [pw_col_coeffs+ 8]
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mova mm0, [pw_col_coeffs+ 0]
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COL_TRANSFORM [dq+sq], mm4, mm0, [pw_col_coeffs+ 8]
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mova mm4, [pw_col_coeffs+ 8]
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lea dq, [dq + 2*sq]
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COL_TRANSFORM [dq], mm6, mm0, mm4
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COL_TRANSFORM [dq+sq], mm7, mm0, mm4
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ret
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; ff_rv34_idct_dc_add_sse4(uint8_t *dst, int stride, int dc);
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%macro RV34_IDCT_DC_ADD 0
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cglobal rv34_idct_dc_add, 3, 3, 6
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; load data
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IDCT_DC_ROUND r2
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pxor m1, m1
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; calculate DC
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movd m0, r2d
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lea r2, [r0+r1*2]
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movd m2, [r0]
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movd m3, [r0+r1]
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pshuflw m0, m0, 0
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movd m4, [r2]
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movd m5, [r2+r1]
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punpcklqdq m0, m0
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punpckldq m2, m3
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punpckldq m4, m5
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punpcklbw m2, m1
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punpcklbw m4, m1
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paddw m2, m0
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paddw m4, m0
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packuswb m2, m4
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movd [r0], m2
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%if cpuflag(sse4)
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pextrd [r0+r1], m2, 1
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pextrd [r2], m2, 2
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pextrd [r2+r1], m2, 3
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%else
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psrldq m2, 4
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movd [r0+r1], m2
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psrldq m2, 4
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movd [r2], m2
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psrldq m2, 4
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movd [r2+r1], m2
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%endif
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RET
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%endmacro
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INIT_XMM sse2
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RV34_IDCT_DC_ADD
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INIT_XMM sse4
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RV34_IDCT_DC_ADD
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