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4e7b5ac48f
C908 X60 vp9_avg_bilin_4hv_8bpp_c : 10.7 9.5 vp9_avg_bilin_4hv_8bpp_rvv_i32 : 4.0 3.5 vp9_avg_bilin_8hv_8bpp_c : 38.5 34.2 vp9_avg_bilin_8hv_8bpp_rvv_i32 : 7.2 6.5 vp9_avg_bilin_16hv_8bpp_c : 147.2 130.5 vp9_avg_bilin_16hv_8bpp_rvv_i32 : 14.5 12.7 vp9_avg_bilin_32hv_8bpp_c : 574.2 509.7 vp9_avg_bilin_32hv_8bpp_rvv_i32 : 42.5 38.0 vp9_avg_bilin_64hv_8bpp_c : 2321.2 2017.7 vp9_avg_bilin_64hv_8bpp_rvv_i32 : 163.5 131.0 vp9_put_bilin_4hv_8bpp_c : 10.0 8.7 vp9_put_bilin_4hv_8bpp_rvv_i32 : 3.5 3.0 vp9_put_bilin_8hv_8bpp_c : 35.2 31.2 vp9_put_bilin_8hv_8bpp_rvv_i32 : 6.5 5.7 vp9_put_bilin_16hv_8bpp_c : 134.0 119.0 vp9_put_bilin_16hv_8bpp_rvv_i32 : 12.7 11.5 vp9_put_bilin_32hv_8bpp_c : 538.5 464.2 vp9_put_bilin_32hv_8bpp_rvv_i32 : 39.7 35.2 vp9_put_bilin_64hv_8bpp_c : 2111.7 1833.2 vp9_put_bilin_64hv_8bpp_rvv_i32 : 138.5 122.5 Signed-off-by: Rémi Denis-Courmont <remi@remlab.net>
209 lines
5.6 KiB
ArmAsm
209 lines
5.6 KiB
ArmAsm
/*
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* Copyright (c) 2024 Institue of Software Chinese Academy of Sciences (ISCAS).
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/riscv/asm.S"
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.macro vsetvlstatic8 len an maxlen mn=m4
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.if \len == 4
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vsetivli zero, \len, e8, mf4, ta, ma
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.elseif \len == 8
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vsetivli zero, \len, e8, mf2, ta, ma
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.elseif \len == 16
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vsetivli zero, \len, e8, m1, ta, ma
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.elseif \len == 32
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li \an, \len
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vsetvli zero, \an, e8, m2, ta, ma
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.elseif \len == 64
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li \an, \maxlen
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vsetvli zero, \an, e8, \mn, ta, ma
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.endif
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.endm
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.macro copy_avg len
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func ff_vp9_avg\len\()_rvv, zve32x
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lpad 0
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csrwi vxrm, 0
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vsetvlstatic8 \len, t0, 64
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1:
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vle8.v v8, (a2)
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vle8.v v16, (a0)
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vaaddu.vv v8, v8, v16
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addi a4, a4, -1
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vse8.v v8, (a0)
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add a2, a2, a3
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add a0, a0, a1
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bnez a4, 1b
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ret
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endfunc
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.endm
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.macro bilin_load dst, mn, type
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.ifc \type,v
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add t4, a2, a3
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.else
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addi t4, a2, 1
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.endif
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vle8.v v4, (a2)
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vle8.v v0, (t4)
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vwmulu.vx v16, v0, \mn
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vwmaccsu.vx v16, t1, v4
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vwadd.wx v16, v16, t3
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vnsra.wi v16, v16, 4
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vadd.vv \dst, v16, v4
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add a2, a2, a3
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.endm
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.macro bilin_h_v op, type, mn
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func ff_\op\()_vp9_bilin_64\type\()_rvv, zve32x
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lpad 0
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vsetvlstatic8 64, t0, 64
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.ifc \op,avg
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csrwi vxrm, 0
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.endif
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li t3, 8
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neg t1, \mn
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1:
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addi a4, a4, -1
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bilin_load v0, \mn, \type
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.ifc \op,avg
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vle8.v v16, (a0)
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vaaddu.vv v0, v0, v16
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.endif
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vse8.v v0, (a0)
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add a0, a0, a1
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bnez a4, 1b
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ret
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.Lbilin_\type\op:
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.ifc \op,avg
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csrwi vxrm, 0
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.endif
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li t4, 8
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neg t1, \mn
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1:
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addi a4, a4, -2
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add t6, a0, a1
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add t0, a2, a3
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vle8.v v8, (a2)
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vle8.v v4, (t0)
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.ifc \type,v
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add t2, t0, a3
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vwmulu.vx v16, v4, \mn
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.else
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addi t3, a2, 1
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addi t2, t0, 1
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vle8.v v0, (t3)
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vwmulu.vx v16, v0, \mn
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.endif
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vle8.v v12, (t2)
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vwmulu.vx v20, v12, \mn
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vwmaccsu.vx v16, t1, v8
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vwmaccsu.vx v20, t1, v4
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vwadd.wx v16, v16, t4
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vwadd.wx v20, v20, t4
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vnsra.wi v16, v16, 4
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vnsra.wi v20, v20, 4
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vadd.vv v0, v16, v8
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vadd.vv v12, v20, v4
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.ifc \op,avg
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vle8.v v16, (a0)
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vle8.v v20, (t6)
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vaaddu.vv v0, v0, v16
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vaaddu.vv v12, v12, v20
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.endif
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vse8.v v0, (a0)
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vse8.v v12, (t6)
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add a2, t0, a3
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add a0, t6, a1
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bnez a4, 1b
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ret
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endfunc
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.endm
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.macro bilin_hv op
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func ff_\op\()_vp9_bilin_64hv_rvv, zve32x
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lpad 0
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vsetvlstatic8 64, t0, 64
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.Lbilin_hv\op:
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.ifc \op,avg
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csrwi vxrm, 0
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.endif
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neg t1, a5
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neg t2, a6
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li t3, 8
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bilin_load v24, a5, h
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1:
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addi a4, a4, -2
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bilin_load v8, a5, h
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vwmulu.vx v16, v8, a6
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vwmaccsu.vx v16, t2, v24
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vwadd.wx v16, v16, t3
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vnsra.wi v16, v16, 4
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vadd.vv v12, v16, v24
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add t5, a0, a1
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bilin_load v24, a5, h
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vwmulu.vx v16, v24, a6
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vwmaccsu.vx v16, t2, v8
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vwadd.wx v16, v16, t3
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vnsra.wi v16, v16, 4
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vadd.vv v0, v16, v8
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.ifc \op,avg
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vle8.v v8, (a0)
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vle8.v v16, (t5)
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vaaddu.vv v12, v12, v8
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vaaddu.vv v0, v0, v16
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.endif
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vse8.v v12, (a0)
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vse8.v v0, (t5)
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add a0, t5, a1
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bnez a4, 1b
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ret
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endfunc
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.endm
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.irp len, 64, 32, 16, 8, 4
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copy_avg \len
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.endr
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bilin_h_v put, h, a5
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bilin_h_v avg, h, a5
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bilin_h_v put, v, a6
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bilin_h_v avg, v, a6
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bilin_hv put
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bilin_hv avg
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.macro func_bilin_h_v len, op, type
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func ff_\op\()_vp9_bilin_\len\()\type\()_rvv, zve32x
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lpad 0
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vsetvlstatic8 \len, t0, 64
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j .Lbilin_\type\()\op
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endfunc
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.endm
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.irp len, 32, 16, 8, 4
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.irp op, put, avg
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.irp type, h, v, hv
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func_bilin_h_v \len, \op, \type
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.endr
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.endr
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.endr
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