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b3fdfc8c4e
FFT in MIPS implementation is working iteratively instead of "recursively" calling functions for smaller FFT sizes. Some of DSP and format convert utils functions are also optimized. Signed-off-by: Nedeljko Babic <nbabic@mips.com> Reviewed-by: Vitor Sessak <vitor1001@gmail.com> Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
339 lines
18 KiB
C
339 lines
18 KiB
C
/*
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* Format Conversion Utils for MIPS
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*
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* Copyright (c) 2012
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* MIPS Technologies, Inc., California.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the MIPS Technologies, Inc., nor the names of is
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE MIPS TECHNOLOGIES, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE MIPS TECHNOLOGIES, INC. BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Author: Zoran Lukic (zoranl@mips.com)
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* Author: Nedeljko Babic (nbabic@mips.com)
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "config.h"
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#include "libavcodec/avcodec.h"
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#include "libavcodec/fmtconvert.h"
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#if HAVE_MIPSDSPR1
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static void float_to_int16_mips(int16_t *dst, const float *src, long len)
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{
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const float *src_end = src + len;
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int ret0, ret1, ret2, ret3, ret4, ret5, ret6, ret7;
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float src0, src1, src2, src3, src4, src5, src6, src7;
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/*
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* loop is 8 times unrolled in assembler in order to achieve better performance
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*/
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__asm__ volatile(
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"beq %[len], $zero, fti16_end%= \n\t"
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"fti16_lp%=: \n\t"
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"lwc1 %[src0], 0(%[src]) \n\t"
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"lwc1 %[src1], 4(%[src]) \n\t"
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"lwc1 %[src2], 8(%[src]) \n\t"
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"lwc1 %[src3], 12(%[src]) \n\t"
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"cvt.w.s %[src0], %[src0] \n\t"
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"cvt.w.s %[src1], %[src1] \n\t"
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"cvt.w.s %[src2], %[src2] \n\t"
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"cvt.w.s %[src3], %[src3] \n\t"
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"mfc1 %[ret0], %[src0] \n\t"
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"mfc1 %[ret1], %[src1] \n\t"
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"mfc1 %[ret2], %[src2] \n\t"
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"mfc1 %[ret3], %[src3] \n\t"
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"lwc1 %[src4], 16(%[src]) \n\t"
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"lwc1 %[src5], 20(%[src]) \n\t"
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"lwc1 %[src6], 24(%[src]) \n\t"
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"lwc1 %[src7], 28(%[src]) \n\t"
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"cvt.w.s %[src4], %[src4] \n\t"
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"cvt.w.s %[src5], %[src5] \n\t"
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"cvt.w.s %[src6], %[src6] \n\t"
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"cvt.w.s %[src7], %[src7] \n\t"
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"addiu %[src], 32 \n\t"
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"shll_s.w %[ret0], %[ret0], 16 \n\t"
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"shll_s.w %[ret1], %[ret1], 16 \n\t"
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"shll_s.w %[ret2], %[ret2], 16 \n\t"
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"shll_s.w %[ret3], %[ret3], 16 \n\t"
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"srl %[ret0], %[ret0], 16 \n\t"
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"srl %[ret1], %[ret1], 16 \n\t"
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"srl %[ret2], %[ret2], 16 \n\t"
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"srl %[ret3], %[ret3], 16 \n\t"
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"sh %[ret0], 0(%[dst]) \n\t"
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"sh %[ret1], 2(%[dst]) \n\t"
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"sh %[ret2], 4(%[dst]) \n\t"
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"sh %[ret3], 6(%[dst]) \n\t"
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"mfc1 %[ret4], %[src4] \n\t"
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"mfc1 %[ret5], %[src5] \n\t"
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"mfc1 %[ret6], %[src6] \n\t"
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"mfc1 %[ret7], %[src7] \n\t"
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"shll_s.w %[ret4], %[ret4], 16 \n\t"
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"shll_s.w %[ret5], %[ret5], 16 \n\t"
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"shll_s.w %[ret6], %[ret6], 16 \n\t"
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"shll_s.w %[ret7], %[ret7], 16 \n\t"
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"srl %[ret4], %[ret4], 16 \n\t"
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"srl %[ret5], %[ret5], 16 \n\t"
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"srl %[ret6], %[ret6], 16 \n\t"
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"srl %[ret7], %[ret7], 16 \n\t"
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"sh %[ret4], 8(%[dst]) \n\t"
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"sh %[ret5], 10(%[dst]) \n\t"
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"sh %[ret6], 12(%[dst]) \n\t"
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"sh %[ret7], 14(%[dst]) \n\t"
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"addiu %[dst], 16 \n\t"
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"bne %[src], %[src_end], fti16_lp%= \n\t"
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"fti16_end%=: \n\t"
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: [ret0]"=&r"(ret0), [ret1]"=&r"(ret1), [ret2]"=&r"(ret2), [ret3]"=&r"(ret3),
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[ret4]"=&r"(ret4), [ret5]"=&r"(ret5), [ret6]"=&r"(ret6), [ret7]"=&r"(ret7),
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[src0]"=&f"(src0), [src1]"=&f"(src1), [src2]"=&f"(src2), [src3]"=&f"(src3),
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[src4]"=&f"(src4), [src5]"=&f"(src5), [src6]"=&f"(src6), [src7]"=&f"(src7),
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[src]"+r"(src), [dst]"+r"(dst)
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: [src_end]"r"(src_end), [len]"r"(len)
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: "memory"
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);
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}
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static void float_to_int16_interleave_mips(int16_t *dst, const float **src, long len,
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int channels)
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{
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int c, ch2 = channels <<1;
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int ret0, ret1, ret2, ret3, ret4, ret5, ret6, ret7;
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float src0, src1, src2, src3, src4, src5, src6, src7;
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int16_t *dst_ptr0, *dst_ptr1, *dst_ptr2, *dst_ptr3;
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int16_t *dst_ptr4, *dst_ptr5, *dst_ptr6, *dst_ptr7;
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const float *src_ptr, *src_ptr2, *src_end;
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if (channels == 2) {
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src_ptr = &src[0][0];
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src_ptr2 = &src[1][0];
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src_end = src_ptr + len;
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__asm__ volatile (
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"fti16i2_lp%=: \n\t"
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"lwc1 %[src0], 0(%[src_ptr]) \n\t"
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"lwc1 %[src1], 0(%[src_ptr2]) \n\t"
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"addiu %[src_ptr], 4 \n\t"
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"cvt.w.s $f9, %[src0] \n\t"
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"cvt.w.s $f10, %[src1] \n\t"
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"mfc1 %[ret0], $f9 \n\t"
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"mfc1 %[ret1], $f10 \n\t"
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"shll_s.w %[ret0], %[ret0], 16 \n\t"
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"shll_s.w %[ret1], %[ret1], 16 \n\t"
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"addiu %[src_ptr2], 4 \n\t"
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"srl %[ret0], %[ret0], 16 \n\t"
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"srl %[ret1], %[ret1], 16 \n\t"
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"sh %[ret0], 0(%[dst]) \n\t"
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"sh %[ret1], 2(%[dst]) \n\t"
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"addiu %[dst], 4 \n\t"
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"bne %[src_ptr], %[src_end], fti16i2_lp%= \n\t"
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: [ret0]"=&r"(ret0), [ret1]"=&r"(ret1),
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[src0]"=&f"(src0), [src1]"=&f"(src1),
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[src_ptr]"+r"(src_ptr), [src_ptr2]"+r"(src_ptr2),
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[dst]"+r"(dst)
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: [src_end]"r"(src_end)
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: "memory"
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);
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} else {
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for (c = 0; c < channels; c++) {
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src_ptr = &src[c][0];
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dst_ptr0 = &dst[c];
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src_end = src_ptr + len;
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/*
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* loop is 8 times unrolled in assembler in order to achieve better performance
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*/
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__asm__ volatile(
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"fti16i_lp%=: \n\t"
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"lwc1 %[src0], 0(%[src_ptr]) \n\t"
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"lwc1 %[src1], 4(%[src_ptr]) \n\t"
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"lwc1 %[src2], 8(%[src_ptr]) \n\t"
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"lwc1 %[src3], 12(%[src_ptr]) \n\t"
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"cvt.w.s %[src0], %[src0] \n\t"
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"cvt.w.s %[src1], %[src1] \n\t"
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"cvt.w.s %[src2], %[src2] \n\t"
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"cvt.w.s %[src3], %[src3] \n\t"
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"mfc1 %[ret0], %[src0] \n\t"
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"mfc1 %[ret1], %[src1] \n\t"
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"mfc1 %[ret2], %[src2] \n\t"
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"mfc1 %[ret3], %[src3] \n\t"
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"lwc1 %[src4], 16(%[src_ptr]) \n\t"
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"lwc1 %[src5], 20(%[src_ptr]) \n\t"
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"lwc1 %[src6], 24(%[src_ptr]) \n\t"
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"lwc1 %[src7], 28(%[src_ptr]) \n\t"
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"addu %[dst_ptr1], %[dst_ptr0], %[ch2] \n\t"
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"addu %[dst_ptr2], %[dst_ptr1], %[ch2] \n\t"
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"addu %[dst_ptr3], %[dst_ptr2], %[ch2] \n\t"
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"addu %[dst_ptr4], %[dst_ptr3], %[ch2] \n\t"
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"addu %[dst_ptr5], %[dst_ptr4], %[ch2] \n\t"
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"addu %[dst_ptr6], %[dst_ptr5], %[ch2] \n\t"
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"addu %[dst_ptr7], %[dst_ptr6], %[ch2] \n\t"
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"addiu %[src_ptr], 32 \n\t"
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"cvt.w.s %[src4], %[src4] \n\t"
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"cvt.w.s %[src5], %[src5] \n\t"
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"cvt.w.s %[src6], %[src6] \n\t"
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"cvt.w.s %[src7], %[src7] \n\t"
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"shll_s.w %[ret0], %[ret0], 16 \n\t"
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"shll_s.w %[ret1], %[ret1], 16 \n\t"
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"shll_s.w %[ret2], %[ret2], 16 \n\t"
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"shll_s.w %[ret3], %[ret3], 16 \n\t"
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"srl %[ret0], %[ret0], 16 \n\t"
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"srl %[ret1], %[ret1], 16 \n\t"
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"srl %[ret2], %[ret2], 16 \n\t"
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"srl %[ret3], %[ret3], 16 \n\t"
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"sh %[ret0], 0(%[dst_ptr0]) \n\t"
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"sh %[ret1], 0(%[dst_ptr1]) \n\t"
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"sh %[ret2], 0(%[dst_ptr2]) \n\t"
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"sh %[ret3], 0(%[dst_ptr3]) \n\t"
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"mfc1 %[ret4], %[src4] \n\t"
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"mfc1 %[ret5], %[src5] \n\t"
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"mfc1 %[ret6], %[src6] \n\t"
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"mfc1 %[ret7], %[src7] \n\t"
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"shll_s.w %[ret4], %[ret4], 16 \n\t"
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"shll_s.w %[ret5], %[ret5], 16 \n\t"
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"shll_s.w %[ret6], %[ret6], 16 \n\t"
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"shll_s.w %[ret7], %[ret7], 16 \n\t"
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"srl %[ret4], %[ret4], 16 \n\t"
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"srl %[ret5], %[ret5], 16 \n\t"
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"srl %[ret6], %[ret6], 16 \n\t"
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"srl %[ret7], %[ret7], 16 \n\t"
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"sh %[ret4], 0(%[dst_ptr4]) \n\t"
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"sh %[ret5], 0(%[dst_ptr5]) \n\t"
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"sh %[ret6], 0(%[dst_ptr6]) \n\t"
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"sh %[ret7], 0(%[dst_ptr7]) \n\t"
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"addu %[dst_ptr0], %[dst_ptr7], %[ch2] \n\t"
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"bne %[src_ptr], %[src_end], fti16i_lp%= \n\t"
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: [ret0]"=&r"(ret0), [ret1]"=&r"(ret1), [ret2]"=&r"(ret2), [ret3]"=&r"(ret3),
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[ret4]"=&r"(ret4), [ret5]"=&r"(ret5), [ret6]"=&r"(ret6), [ret7]"=&r"(ret7),
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[src0]"=&f"(src0), [src1]"=&f"(src1), [src2]"=&f"(src2), [src3]"=&f"(src3),
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[src4]"=&f"(src4), [src5]"=&f"(src5), [src6]"=&f"(src6), [src7]"=&f"(src7),
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[dst_ptr1]"=&r"(dst_ptr1), [dst_ptr2]"=&r"(dst_ptr2), [dst_ptr3]"=&r"(dst_ptr3),
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[dst_ptr4]"=&r"(dst_ptr4), [dst_ptr5]"=&r"(dst_ptr5), [dst_ptr6]"=&r"(dst_ptr6),
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[dst_ptr7]"=&r"(dst_ptr7), [dst_ptr0]"+r"(dst_ptr0), [src_ptr]"+r"(src_ptr)
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: [ch2]"r"(ch2), [src_end]"r"(src_end)
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: "memory"
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);
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}
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}
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}
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#endif /* HAVE_MIPSDSPR1 */
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static void int32_to_float_fmul_scalar_mips(float *dst, const int *src,
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float mul, int len)
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{
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/*
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* variables used in inline assembler
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*/
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float temp1, temp3, temp5, temp7, temp9, temp11, temp13, temp15;
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int rpom1, rpom2, rpom11, rpom21, rpom12, rpom22, rpom13, rpom23;
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const int *src_end = src + len;
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/*
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* loop is 8 times unrolled in assembler in order to achieve better performance
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*/
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__asm__ volatile (
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"i32tf_lp%=: \n\t"
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"lw %[rpom11], 0(%[src]) \n\t"
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"lw %[rpom21], 4(%[src]) \n\t"
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"lw %[rpom1], 8(%[src]) \n\t"
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"lw %[rpom2], 12(%[src]) \n\t"
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"mtc1 %[rpom11], %[temp1] \n\t"
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"mtc1 %[rpom21], %[temp3] \n\t"
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"mtc1 %[rpom1], %[temp5] \n\t"
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"mtc1 %[rpom2], %[temp7] \n\t"
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"lw %[rpom13], 16(%[src]) \n\t"
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"lw %[rpom23], 20(%[src]) \n\t"
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"lw %[rpom12], 24(%[src]) \n\t"
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"lw %[rpom22], 28(%[src]) \n\t"
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"mtc1 %[rpom13], %[temp9] \n\t"
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"mtc1 %[rpom23], %[temp11] \n\t"
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"mtc1 %[rpom12], %[temp13] \n\t"
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"mtc1 %[rpom22], %[temp15] \n\t"
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"addiu %[src], 32 \n\t"
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"cvt.s.w %[temp1], %[temp1] \n\t"
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"cvt.s.w %[temp3], %[temp3] \n\t"
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"cvt.s.w %[temp5], %[temp5] \n\t"
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"cvt.s.w %[temp7], %[temp7] \n\t"
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"cvt.s.w %[temp9], %[temp9] \n\t"
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"cvt.s.w %[temp11], %[temp11] \n\t"
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"cvt.s.w %[temp13], %[temp13] \n\t"
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"cvt.s.w %[temp15], %[temp15] \n\t"
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"mul.s %[temp1], %[temp1], %[mul] \n\t"
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"mul.s %[temp3], %[temp3], %[mul] \n\t"
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"mul.s %[temp5], %[temp5], %[mul] \n\t"
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"mul.s %[temp7], %[temp7], %[mul] \n\t"
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"mul.s %[temp9], %[temp9], %[mul] \n\t"
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"mul.s %[temp11], %[temp11], %[mul] \n\t"
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"mul.s %[temp13], %[temp13], %[mul] \n\t"
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"mul.s %[temp15], %[temp15], %[mul] \n\t"
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"swc1 %[temp1], 0(%[dst]) \n\t" /*dst[i] = src[i] * mul; */
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"swc1 %[temp3], 4(%[dst]) \n\t" /*dst[i+1] = src[i+1] * mul;*/
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"swc1 %[temp5], 8(%[dst]) \n\t" /*dst[i+2] = src[i+2] * mul;*/
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"swc1 %[temp7], 12(%[dst]) \n\t" /*dst[i+3] = src[i+3] * mul;*/
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"swc1 %[temp9], 16(%[dst]) \n\t" /*dst[i+4] = src[i+4] * mul;*/
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"swc1 %[temp11], 20(%[dst]) \n\t" /*dst[i+5] = src[i+5] * mul;*/
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"swc1 %[temp13], 24(%[dst]) \n\t" /*dst[i+6] = src[i+6] * mul;*/
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"swc1 %[temp15], 28(%[dst]) \n\t" /*dst[i+7] = src[i+7] * mul;*/
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"addiu %[dst], 32 \n\t"
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"bne %[src], %[src_end], i32tf_lp%= \n\t"
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: [temp1]"=&f"(temp1), [temp11]"=&f"(temp11),
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[temp13]"=&f"(temp13), [temp15]"=&f"(temp15),
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[temp3]"=&f"(temp3), [temp5]"=&f"(temp5),
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[temp7]"=&f"(temp7), [temp9]"=&f"(temp9),
|
|
[rpom1]"=&r"(rpom1), [rpom2]"=&r"(rpom2),
|
|
[rpom11]"=&r"(rpom11), [rpom21]"=&r"(rpom21),
|
|
[rpom12]"=&r"(rpom12), [rpom22]"=&r"(rpom22),
|
|
[rpom13]"=&r"(rpom13), [rpom23]"=&r"(rpom23),
|
|
[dst]"+r"(dst), [src]"+r"(src)
|
|
: [mul]"f"(mul), [src_end]"r"(src_end)
|
|
: "memory"
|
|
);
|
|
}
|
|
|
|
av_cold void ff_fmt_convert_init_mips(FmtConvertContext *c)
|
|
{
|
|
#if HAVE_MIPSDSPR1
|
|
c->float_to_int16_interleave = float_to_int16_interleave_mips;
|
|
c->float_to_int16 = float_to_int16_mips;
|
|
#endif
|
|
c->int32_to_float_fmul_scalar = int32_to_float_fmul_scalar_mips;
|
|
}
|