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https://git.ffmpeg.org/ffmpeg.git
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bbe95f7353
From x86inc: > On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either > a branch or a branch target. So switch to a 2-byte form of ret in that case. > We can automatically detect "follows a branch", but not a branch target. > (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.) x86inc can automatically determine whether to use REP_RET rather than REP in most of these cases, so impact is minimal. Additionally, a few REP_RETs were used unnecessary, despite the return being nowhere near a branch. The only CPUs affected were AMD K10s, made between 2007 and 2011, 16 years ago and 12 years ago, respectively. In the future, everyone involved with x86inc should consider dropping REP_RETs altogether.
144 lines
3.8 KiB
NASM
144 lines
3.8 KiB
NASM
;******************************************************************************
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;* SIMD-optimized HuffYUV functions
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;* Copyright (c) 2008 Loren Merritt
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;* Copyright (c) 2014 Christophe Gisquet
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "libavutil/x86/x86util.asm"
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SECTION .text
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%include "libavcodec/x86/huffyuvdsp_template.asm"
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;------------------------------------------------------------------------------
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; void (*add_int16)(uint16_t *dst, const uint16_t *src, unsigned mask, int w);
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;------------------------------------------------------------------------------
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%macro ADD_INT16 0
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cglobal add_int16, 4,4,5, dst, src, mask, w, tmp
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test srcq, mmsize-1
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jnz .unaligned
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test dstq, mmsize-1
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jnz .unaligned
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INT16_LOOP a, add
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.unaligned:
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INT16_LOOP u, add
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%endmacro
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INIT_XMM sse2
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ADD_INT16
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%if HAVE_AVX2_EXTERNAL
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INIT_YMM avx2
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ADD_INT16
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%endif
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; void add_hfyu_left_pred_bgr32(uint8_t *dst, const uint8_t *src,
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; intptr_t w, uint8_t *left)
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INIT_XMM sse2
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cglobal add_hfyu_left_pred_bgr32, 4,4,3, dst, src, w, left
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shl wq, 2
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movd m0, [leftq]
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lea dstq, [dstq + wq]
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lea srcq, [srcq + wq]
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LSHIFT m0, mmsize-4
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neg wq
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.loop:
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movu m1, [srcq+wq]
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mova m2, m1
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LSHIFT m1, 4
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paddb m1, m2
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pshufd m0, m0, q3333
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mova m2, m1
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LSHIFT m1, 8
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paddb m1, m2
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paddb m0, m1
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movu [dstq+wq], m0
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add wq, mmsize
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jl .loop
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movd m0, [dstq-4]
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movd [leftq], m0
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RET
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; void add_hfyu_median_prediction_mmxext(uint8_t *dst, const uint8_t *top, const uint8_t *diff, int mask, int w, int *left, int *left_top)
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INIT_MMX mmxext
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cglobal add_hfyu_median_pred_int16, 7,7,0, dst, top, diff, mask, w, left, left_top
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add wd, wd
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movd mm6, maskd
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SPLATW mm6, mm6
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movq mm0, [topq]
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movq mm2, mm0
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movd mm4, [left_topq]
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psllq mm2, 16
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movq mm1, mm0
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por mm4, mm2
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movd mm3, [leftq]
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psubw mm0, mm4 ; t-tl
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add dstq, wq
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add topq, wq
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add diffq, wq
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neg wq
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jmp .skip
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.loop:
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movq mm4, [topq+wq]
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movq mm0, mm4
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psllq mm4, 16
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por mm4, mm1
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movq mm1, mm0 ; t
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psubw mm0, mm4 ; t-tl
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.skip:
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movq mm2, [diffq+wq]
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%assign i 0
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%rep 4
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movq mm4, mm0
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paddw mm4, mm3 ; t-tl+l
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pand mm4, mm6
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movq mm5, mm3
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pmaxsw mm3, mm1
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pminsw mm5, mm1
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pminsw mm3, mm4
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pmaxsw mm3, mm5 ; median
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paddw mm3, mm2 ; +residual
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pand mm3, mm6
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%if i==0
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movq mm7, mm3
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psllq mm7, 48
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%else
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movq mm4, mm3
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psrlq mm7, 16
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psllq mm4, 48
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por mm7, mm4
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%endif
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%if i<3
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psrlq mm0, 16
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psrlq mm1, 16
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psrlq mm2, 16
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%endif
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%assign i i+1
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%endrep
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movq [dstq+wq], mm7
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add wq, 8
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jl .loop
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movzx r2d, word [dstq-2]
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mov [leftq], r2d
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movzx r2d, word [topq-2]
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mov [left_topq], r2d
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RET
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