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6766169c41
Just like gcc 4.6 and later on ARM, gcc 4.8 on MIPS generates inefficient code when a known-unaligned location is used as a memory input operand. This applies the same fix as has been previously done to the ARM version of the code. Signed-off-by: Mans Rullgard <mans@mansr.com>
47 lines
1.5 KiB
C
47 lines
1.5 KiB
C
/*
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* Copyright (c) 2009 Mans Rullgard <mans@mansr.com>
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*
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* This file is part of Libav.
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*
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* Libav is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* Libav is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with Libav; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef AVUTIL_MIPS_INTREADWRITE_H
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#define AVUTIL_MIPS_INTREADWRITE_H
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#include <stdint.h>
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#include "config.h"
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#if ARCH_MIPS64 && HAVE_INLINE_ASM
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#define AV_RN32 AV_RN32
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static av_always_inline uint32_t AV_RN32(const void *p)
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{
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struct __attribute__((packed)) u32 { uint32_t v; };
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const uint8_t *q = p;
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const struct u32 *pl = (const struct u32 *)(q + 3 * !HAVE_BIGENDIAN);
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const struct u32 *pr = (const struct u32 *)(q + 3 * HAVE_BIGENDIAN);
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uint32_t v;
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__asm__ ("lwl %0, %1 \n\t"
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"lwr %0, %2 \n\t"
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: "=&r"(v)
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: "m"(*pl), "m"(*pr));
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return v;
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}
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#endif /* ARCH_MIPS64 && HAVE_INLINE_ASM */
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#endif /* AVUTIL_MIPS_INTREADWRITE_H */
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