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0c0a3deb18
RVV defines a total of 12 different extensions, including: - 5 different instruction subsets: - Zve32x: 8-, 16- and 32-bit integers, - Zve32f: Zve32x plus single precision floats, - Zve64x: Zve32x plus 64-bit integers, - Zve64f: Zve32f plus Zve64x, - Zve64d: Zve64f plus double precision floats. - 6 different vector lengths: - Zvl32b (embedded only), - Zvl64b (embedded only), - Zvl128b, - Zvl256b, - Zvl512b, - Zvl1024b, - and the V extension proper: equivalent to Zve64f and Zvl128b. In total, there are 6 different possible sets of supported instructions (including the empty set), but for convenience we allocate one bit for each type sets: up-to-32-bit ints (RVV_I32), floats (RVV_F32), 64-bit ints (RVV_I64) and doubles (RVV_F64). Whence the vector size is needed, it can be retrieved by reading the unprivileged read-only vlenb CSR. This should probably be a separate helper macro if needed at a later point.
76 lines
2.1 KiB
C
76 lines
2.1 KiB
C
/*
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* Copyright © 2022 Rémi Denis-Courmont.
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/cpu.h"
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#include "libavutil/cpu_internal.h"
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#include "libavutil/log.h"
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#include "config.h"
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#if HAVE_GETAUXVAL
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#include <sys/auxv.h>
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#define HWCAP_RV(letter) (1ul << ((letter) - 'A'))
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#endif
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int ff_get_cpu_flags_riscv(void)
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{
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int ret = 0;
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#if HAVE_GETAUXVAL
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const unsigned long hwcap = getauxval(AT_HWCAP);
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if (hwcap & HWCAP_RV('I'))
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ret |= AV_CPU_FLAG_RVI;
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if (hwcap & HWCAP_RV('F'))
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ret |= AV_CPU_FLAG_RVF;
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if (hwcap & HWCAP_RV('D'))
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ret |= AV_CPU_FLAG_RVD;
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/* The V extension implies all Zve* functional subsets */
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if (hwcap & HWCAP_RV('V'))
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ret |= AV_CPU_FLAG_RVV_I32 | AV_CPU_FLAG_RVV_I64
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| AV_CPU_FLAG_RVV_F32 | AV_CPU_FLAG_RVV_F64;
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#endif
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#ifdef __riscv_i
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ret |= AV_CPU_FLAG_RVI;
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#endif
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#if defined (__riscv_flen) && (__riscv_flen >= 32)
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ret |= AV_CPU_FLAG_RVF;
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#if (__riscv_flen >= 64)
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ret |= AV_CPU_FLAG_RVD;
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#endif
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#endif
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/* If RV-V is enabled statically at compile-time, check the details. */
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#ifdef __riscv_vectors
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ret |= AV_CPU_FLAG_RVV_I32;
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#if __riscv_v_elen >= 64
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ret |= AV_CPU_FLAG_RVV_I64;
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#endif
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#if __riscv_v_elen_fp >= 32
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ret |= AV_CPU_FLAG_RVV_F32;
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#if __riscv_v_elen_fp >= 64
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ret |= AV_CPU_FLAG_RVV_F64;
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#endif
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#endif
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#endif
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return ret;
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}
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