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https://git.ffmpeg.org/ffmpeg.git
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bbe95f7353
From x86inc: > On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either > a branch or a branch target. So switch to a 2-byte form of ret in that case. > We can automatically detect "follows a branch", but not a branch target. > (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.) x86inc can automatically determine whether to use REP_RET rather than REP in most of these cases, so impact is minimal. Additionally, a few REP_RETs were used unnecessary, despite the return being nowhere near a branch. The only CPUs affected were AMD K10s, made between 2007 and 2011, 16 years ago and 12 years ago, respectively. In the future, everyone involved with x86inc should consider dropping REP_RETs altogether.
285 lines
6.2 KiB
NASM
285 lines
6.2 KiB
NASM
;*****************************************************************************
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;* MMX/SSE2/AVX-optimized 10-bit H.264 weighted prediction code
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;*****************************************************************************
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;* Copyright (C) 2005-2011 x264 project
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;*
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;* Authors: Daniel Kang <daniel.d.kang@gmail.com>
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "libavutil/x86/x86util.asm"
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SECTION_RODATA 32
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sq_1: dq 1
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dq 0
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cextern pw_1
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cextern pw_1023
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%define pw_pixel_max pw_1023
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SECTION .text
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;-----------------------------------------------------------------------------
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; void ff_h264_weight_16_10(uint8_t *dst, int stride, int height,
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; int log2_denom, int weight, int offset);
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;-----------------------------------------------------------------------------
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%macro WEIGHT_PROLOGUE 0
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.prologue:
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PROLOGUE 0,6,8
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movifnidn r0, r0mp
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movifnidn r1d, r1m
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movifnidn r2d, r2m
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movifnidn r4d, r4m
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movifnidn r5d, r5m
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%endmacro
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%macro WEIGHT_SETUP 0
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mova m0, [pw_1]
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movd m2, r3m
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pslld m0, m2 ; 1<<log2_denom
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SPLATW m0, m0
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shl r5, 19 ; *8, move to upper half of dword
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lea r5, [r5+r4*2+0x10000]
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movd m3, r5d ; weight<<1 | 1+(offset<<(3))
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pshufd m3, m3, 0
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mova m4, [pw_pixel_max]
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paddw m2, [sq_1] ; log2_denom+1
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%if notcpuflag(sse4)
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pxor m7, m7
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%endif
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%endmacro
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%macro WEIGHT_OP 1-2
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%if %0==1
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mova m5, [r0+%1]
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punpckhwd m6, m5, m0
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punpcklwd m5, m0
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%else
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movq m5, [r0+%1]
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movq m6, [r0+%2]
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punpcklwd m5, m0
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punpcklwd m6, m0
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%endif
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pmaddwd m5, m3
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pmaddwd m6, m3
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psrad m5, m2
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psrad m6, m2
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%if cpuflag(sse4)
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packusdw m5, m6
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pminsw m5, m4
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%else
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packssdw m5, m6
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CLIPW m5, m7, m4
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%endif
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%endmacro
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%macro WEIGHT_FUNC_DBL 0
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cglobal h264_weight_16_10
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WEIGHT_PROLOGUE
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WEIGHT_SETUP
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.nextrow:
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WEIGHT_OP 0
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mova [r0 ], m5
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WEIGHT_OP 16
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mova [r0+16], m5
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add r0, r1
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dec r2d
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jnz .nextrow
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RET
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%endmacro
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INIT_XMM sse2
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WEIGHT_FUNC_DBL
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INIT_XMM sse4
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WEIGHT_FUNC_DBL
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%macro WEIGHT_FUNC_MM 0
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cglobal h264_weight_8_10
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WEIGHT_PROLOGUE
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WEIGHT_SETUP
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.nextrow:
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WEIGHT_OP 0
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mova [r0], m5
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add r0, r1
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dec r2d
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jnz .nextrow
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RET
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%endmacro
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INIT_XMM sse2
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WEIGHT_FUNC_MM
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INIT_XMM sse4
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WEIGHT_FUNC_MM
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%macro WEIGHT_FUNC_HALF_MM 0
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cglobal h264_weight_4_10
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WEIGHT_PROLOGUE
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sar r2d, 1
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WEIGHT_SETUP
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lea r3, [r1*2]
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.nextrow:
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WEIGHT_OP 0, r1
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movh [r0], m5
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movhps [r0+r1], m5
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add r0, r3
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dec r2d
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jnz .nextrow
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RET
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%endmacro
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INIT_XMM sse2
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WEIGHT_FUNC_HALF_MM
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INIT_XMM sse4
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WEIGHT_FUNC_HALF_MM
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;-----------------------------------------------------------------------------
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; void ff_h264_biweight_16_10(uint8_t *dst, uint8_t *src, int stride,
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; int height, int log2_denom, int weightd,
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; int weights, int offset);
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;-----------------------------------------------------------------------------
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%if ARCH_X86_32
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DECLARE_REG_TMP 3
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%else
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DECLARE_REG_TMP 7
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%endif
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%macro BIWEIGHT_PROLOGUE 0
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.prologue:
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PROLOGUE 0,8,8
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movifnidn r0, r0mp
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movifnidn r1, r1mp
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movifnidn r2d, r2m
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movifnidn r5d, r5m
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movifnidn r6d, r6m
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movifnidn t0d, r7m
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%endmacro
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%macro BIWEIGHT_SETUP 0
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lea t0, [t0*4+1] ; (offset<<2)+1
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or t0, 1
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shl r6, 16
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or r5, r6
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movd m4, r5d ; weightd | weights
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movd m5, t0d ; (offset+1)|1
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movd m6, r4m ; log2_denom
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pslld m5, m6 ; (((offset<<2)+1)|1)<<log2_denom
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paddd m6, [sq_1]
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pshufd m4, m4, 0
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pshufd m5, m5, 0
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mova m3, [pw_pixel_max]
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movifnidn r3d, r3m
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%if notcpuflag(sse4)
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pxor m7, m7
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%endif
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%endmacro
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%macro BIWEIGHT 1-2
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%if %0==1
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mova m0, [r0+%1]
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mova m1, [r1+%1]
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punpckhwd m2, m0, m1
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punpcklwd m0, m1
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%else
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movq m0, [r0+%1]
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movq m1, [r1+%1]
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punpcklwd m0, m1
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movq m2, [r0+%2]
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movq m1, [r1+%2]
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punpcklwd m2, m1
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%endif
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pmaddwd m0, m4
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pmaddwd m2, m4
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paddd m0, m5
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paddd m2, m5
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psrad m0, m6
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psrad m2, m6
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%if cpuflag(sse4)
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packusdw m0, m2
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pminsw m0, m3
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%else
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packssdw m0, m2
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CLIPW m0, m7, m3
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%endif
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%endmacro
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%macro BIWEIGHT_FUNC_DBL 0
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cglobal h264_biweight_16_10
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BIWEIGHT_PROLOGUE
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BIWEIGHT_SETUP
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.nextrow:
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BIWEIGHT 0
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mova [r0 ], m0
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BIWEIGHT 16
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mova [r0+16], m0
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add r0, r2
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add r1, r2
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dec r3d
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jnz .nextrow
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RET
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%endmacro
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INIT_XMM sse2
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BIWEIGHT_FUNC_DBL
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INIT_XMM sse4
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BIWEIGHT_FUNC_DBL
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%macro BIWEIGHT_FUNC 0
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cglobal h264_biweight_8_10
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BIWEIGHT_PROLOGUE
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BIWEIGHT_SETUP
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.nextrow:
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BIWEIGHT 0
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mova [r0], m0
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add r0, r2
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add r1, r2
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dec r3d
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jnz .nextrow
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RET
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%endmacro
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INIT_XMM sse2
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BIWEIGHT_FUNC
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INIT_XMM sse4
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BIWEIGHT_FUNC
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%macro BIWEIGHT_FUNC_HALF 0
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cglobal h264_biweight_4_10
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BIWEIGHT_PROLOGUE
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BIWEIGHT_SETUP
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sar r3d, 1
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lea r4, [r2*2]
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.nextrow:
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BIWEIGHT 0, r2
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movh [r0 ], m0
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movhps [r0+r2], m0
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add r0, r4
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add r1, r4
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dec r3d
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jnz .nextrow
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RET
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%endmacro
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INIT_XMM sse2
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BIWEIGHT_FUNC_HALF
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INIT_XMM sse4
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BIWEIGHT_FUNC_HALF
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