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lavu/riscv: add CPU flag for B bit manipulations
The B extension was finally ratified in May 2024, encompassing: - Zba (addresses), - Zbb (basics) and - Zbs (single bits). It does not include Zbc (base-2 polynomials).
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@ -2,6 +2,9 @@ The last version increases of all libraries were on 2024-03-07
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API changes, most recent first:
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2024-07-25 - xxxxxxxxx - lavu 59.29.100 - cpu.h
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Add AV_CPU_FLAG_RVB.
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2024-07-xx - xxxxxxxxxx - lavf 61 - avformat.h
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Deprecate avformat_transfer_internal_stream_timing_info()
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and av_stream_get_codec_timebase() without replacement.
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@ -186,6 +186,7 @@ int av_parse_cpu_caps(unsigned *flags, const char *s)
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{ "rvi", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVI }, .unit = "flags" },
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{ "rvf", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVF }, .unit = "flags" },
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{ "rvd", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVD }, .unit = "flags" },
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{ "rvb", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB }, .unit = "flags" },
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{ "zve32x", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_I32 }, .unit = "flags" },
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{ "zve32f", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F32 }, .unit = "flags" },
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{ "zve64x", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_I64 }, .unit = "flags" },
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@ -92,6 +92,7 @@
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#define AV_CPU_FLAG_RVB_ADDR (1 << 8) ///< Address bit-manipulations
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#define AV_CPU_FLAG_RV_ZVBB (1 << 9) ///< Vector basic bit-manipulations
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#define AV_CPU_FLAG_RV_MISALIGNED (1 <<10) ///< Fast misaligned accesses
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#define AV_CPU_FLAG_RVB (1 <<11) ///< B (bit manipulations)
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/**
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* Return the flags which specify extensions supported by the CPU.
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@ -72,6 +72,12 @@ int ff_get_cpu_flags_riscv(void)
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#ifdef RISCV_HWPROBE_EXT_ZBB
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if (pairs[1].value & RISCV_HWPROBE_EXT_ZBB)
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ret |= AV_CPU_FLAG_RVB_BASIC;
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#if defined (RISCV_HWPROBE_EXT_ZBA) && defined (RISCV_HWPROBE_EXT_ZBS)
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if ((pairs[1].value & RISCV_HWPROBE_EXT_ZBA) &&
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(pairs[1].value & RISCV_HWPROBE_EXT_ZBB) &&
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(pairs[1].value & RISCV_HWPROBE_EXT_ZBS))
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ret |= AV_CPU_FLAG_RVB;
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#endif
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#endif
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#ifdef RISCV_HWPROBE_EXT_ZVBB
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if (pairs[1].value & RISCV_HWPROBE_EXT_ZVBB)
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@ -94,6 +100,9 @@ int ff_get_cpu_flags_riscv(void)
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ret |= AV_CPU_FLAG_RVF;
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if (hwcap & HWCAP_RV('D'))
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ret |= AV_CPU_FLAG_RVD;
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if (hwcap & HWCAP_RV('B'))
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ret |= AV_CPU_FLAG_RVB_ADDR | AV_CPU_FLAG_RVB_BASIC |
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AV_CPU_FLAG_RVB;
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/* The V extension implies all Zve* functional subsets */
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if (hwcap & HWCAP_RV('V'))
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@ -118,6 +127,10 @@ int ff_get_cpu_flags_riscv(void)
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#ifdef __riscv_zbb
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ret |= AV_CPU_FLAG_RVB_BASIC;
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#endif
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#if defined (__riscv_b) || \
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(defined (__riscv_zba) && defined (__riscv_zbb) && defined (__riscv_zbs))
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ret |= AV_CPU_FLAG_RVB;
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#endif
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/* If RV-V is enabled statically at compile-time, check the details. */
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#ifdef __riscv_vector
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@ -90,6 +90,7 @@ static const struct {
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{ AV_CPU_FLAG_RVD, "rvd" },
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{ AV_CPU_FLAG_RVB_ADDR, "zba" },
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{ AV_CPU_FLAG_RVB_BASIC, "zbb" },
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{ AV_CPU_FLAG_RVB, "rvb" },
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{ AV_CPU_FLAG_RVV_I32, "zve32x" },
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{ AV_CPU_FLAG_RVV_F32, "zve32f" },
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{ AV_CPU_FLAG_RVV_I64, "zve64x" },
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@ -79,7 +79,7 @@
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*/
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#define LIBAVUTIL_VERSION_MAJOR 59
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#define LIBAVUTIL_VERSION_MINOR 28
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#define LIBAVUTIL_VERSION_MINOR 29
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#define LIBAVUTIL_VERSION_MICRO 100
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#define LIBAVUTIL_VERSION_INT AV_VERSION_INT(LIBAVUTIL_VERSION_MAJOR, \
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@ -295,6 +295,7 @@ static const struct {
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{ "RVD", "rvd", AV_CPU_FLAG_RVD },
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{ "RVBaddr", "rvb_a", AV_CPU_FLAG_RVB_ADDR },
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{ "RVBbasic", "rvb_b", AV_CPU_FLAG_RVB_BASIC },
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{ "RVB", "rvb", AV_CPU_FLAG_RVB },
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{ "RVVi32", "rvv_i32", AV_CPU_FLAG_RVV_I32 },
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{ "RVVf32", "rvv_f32", AV_CPU_FLAG_RVV_F32 },
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{ "RVVi64", "rvv_i64", AV_CPU_FLAG_RVV_I64 },
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